2022-01-05 19:10:18 +03:00
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#include <furi_hal_i2c.h>
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2022-03-30 18:23:40 +03:00
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#include <furi_hal_delay.h>
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2022-01-05 19:10:18 +03:00
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#include <furi_hal_version.h>
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[FL-2399, FL-2261] Tickless sleep shenanigans (#1168)
* Disable USART in sleep
* Restore UART state on suspend/resume
* FuriHal: Enable stop mode and add insomnia to I2C and SPI
* Remove IDLE interrupt
* FuriHal: add FPU isr and disable all FPU interrupt, add core2 stop mode configuration on deep sleep
* FuriHal: tie stop mode debug with debug rtc flag
* FuriHal: adjust flash latency on clock switch, tie mcu debug with RTC debug flag
* FuriHal: move resource init to early stage
* Add EXTI pending check, enable debug traps with compile-time flag
* Wrap sleep debug functions in conditional compilation
* Remove erroneous changed
* Do not use CSS, remove it from everywhere
* Enable/disable USB on VBUS connect (prototype)
* FuriHal: add LPMS and DEEPSLEEP magic, workaround state inconsistency between cores
* FuriHal: honor c1 LMPS
* USB mode switch fix
* Applications: add flags and insomnia bypass system
* Correct spelling
* FuriHal: cleanup insomnia usage, reset sleep flags on wakeup, add shutdown api
* FuriHal: extra check on reinit request
* FuriHal: rename gpio_display_rst pin to gpio_display_rst_n
* FuriHal: add debug HAL
* FuriHal: add some magic to core2 reload procedure, fix issue with crash on ble keyboard exit
* FuriHal: cleanup ble glue, add BLE_GLUE_DEBUG flag
* FuriHal: ble reinit API, move os timer to LPTIM1 for deep sleep capability, shutdown that works
* FuriHal: take insomnia while shutdown
* Remove USB switch on/off on VBUS change
* Better tick skew handling
* Improve tick consistency under load
* Add USB_HP dummy IRQ handler
* Move interrupt check closer to sleep
* Clean up includes
* Re-enable Insomnia globally
* FuriHal: enable CSS
* FuriHal: remove questionable core2 clock shenanigans
* FuriHal: use core1 RCC registers in idle timer config
* FuriHal: return back CSS handlers, add lptim isr dispatching
Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
Co-authored-by: nminaylov <nm29719@gmail.com>
2022-04-29 16:29:51 +03:00
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#include <furi_hal_power.h>
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2021-07-22 11:44:15 +03:00
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2021-05-18 12:23:14 +03:00
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#include <stm32wbxx_ll_i2c.h>
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#include <stm32wbxx_ll_gpio.h>
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#include <stm32wbxx_ll_cortex.h>
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#include <furi.h>
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2021-11-12 16:04:35 +03:00
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#define TAG "FuriHalI2C"
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2022-04-13 23:50:25 +03:00
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void furi_hal_i2c_init_early() {
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2021-11-28 21:28:19 +03:00
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furi_hal_i2c_bus_power.callback(&furi_hal_i2c_bus_power, FuriHalI2cBusEventInit);
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2022-04-13 23:50:25 +03:00
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}
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void furi_hal_i2c_deinit_early() {
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furi_hal_i2c_bus_power.callback(&furi_hal_i2c_bus_power, FuriHalI2cBusEventDeinit);
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}
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void furi_hal_i2c_init() {
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2021-11-28 21:28:19 +03:00
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furi_hal_i2c_bus_external.callback(&furi_hal_i2c_bus_external, FuriHalI2cBusEventInit);
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2021-11-12 16:04:35 +03:00
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FURI_LOG_I(TAG, "Init OK");
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2021-05-18 12:23:14 +03:00
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}
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2021-11-28 21:28:19 +03:00
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void furi_hal_i2c_acquire(FuriHalI2cBusHandle* handle) {
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[FL-2399, FL-2261] Tickless sleep shenanigans (#1168)
* Disable USART in sleep
* Restore UART state on suspend/resume
* FuriHal: Enable stop mode and add insomnia to I2C and SPI
* Remove IDLE interrupt
* FuriHal: add FPU isr and disable all FPU interrupt, add core2 stop mode configuration on deep sleep
* FuriHal: tie stop mode debug with debug rtc flag
* FuriHal: adjust flash latency on clock switch, tie mcu debug with RTC debug flag
* FuriHal: move resource init to early stage
* Add EXTI pending check, enable debug traps with compile-time flag
* Wrap sleep debug functions in conditional compilation
* Remove erroneous changed
* Do not use CSS, remove it from everywhere
* Enable/disable USB on VBUS connect (prototype)
* FuriHal: add LPMS and DEEPSLEEP magic, workaround state inconsistency between cores
* FuriHal: honor c1 LMPS
* USB mode switch fix
* Applications: add flags and insomnia bypass system
* Correct spelling
* FuriHal: cleanup insomnia usage, reset sleep flags on wakeup, add shutdown api
* FuriHal: extra check on reinit request
* FuriHal: rename gpio_display_rst pin to gpio_display_rst_n
* FuriHal: add debug HAL
* FuriHal: add some magic to core2 reload procedure, fix issue with crash on ble keyboard exit
* FuriHal: cleanup ble glue, add BLE_GLUE_DEBUG flag
* FuriHal: ble reinit API, move os timer to LPTIM1 for deep sleep capability, shutdown that works
* FuriHal: take insomnia while shutdown
* Remove USB switch on/off on VBUS change
* Better tick skew handling
* Improve tick consistency under load
* Add USB_HP dummy IRQ handler
* Move interrupt check closer to sleep
* Clean up includes
* Re-enable Insomnia globally
* FuriHal: enable CSS
* FuriHal: remove questionable core2 clock shenanigans
* FuriHal: use core1 RCC registers in idle timer config
* FuriHal: return back CSS handlers, add lptim isr dispatching
Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
Co-authored-by: nminaylov <nm29719@gmail.com>
2022-04-29 16:29:51 +03:00
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furi_hal_power_insomnia_enter();
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2021-11-28 21:28:19 +03:00
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// Lock bus access
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handle->bus->callback(handle->bus, FuriHalI2cBusEventLock);
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// Ensuree that no active handle set
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furi_check(handle->bus->current_handle == NULL);
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// Set current handle
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handle->bus->current_handle = handle;
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// Activate bus
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handle->bus->callback(handle->bus, FuriHalI2cBusEventActivate);
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// Activate handle
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handle->callback(handle, FuriHalI2cBusHandleEventActivate);
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}
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void furi_hal_i2c_release(FuriHalI2cBusHandle* handle) {
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// Ensure that current handle is our handle
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furi_check(handle->bus->current_handle == handle);
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// Deactivate handle
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handle->callback(handle, FuriHalI2cBusHandleEventDeactivate);
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// Deactivate bus
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handle->bus->callback(handle->bus, FuriHalI2cBusEventDeactivate);
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// Reset current handle
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handle->bus->current_handle = NULL;
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// Unlock bus
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handle->bus->callback(handle->bus, FuriHalI2cBusEventUnlock);
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[FL-2399, FL-2261] Tickless sleep shenanigans (#1168)
* Disable USART in sleep
* Restore UART state on suspend/resume
* FuriHal: Enable stop mode and add insomnia to I2C and SPI
* Remove IDLE interrupt
* FuriHal: add FPU isr and disable all FPU interrupt, add core2 stop mode configuration on deep sleep
* FuriHal: tie stop mode debug with debug rtc flag
* FuriHal: adjust flash latency on clock switch, tie mcu debug with RTC debug flag
* FuriHal: move resource init to early stage
* Add EXTI pending check, enable debug traps with compile-time flag
* Wrap sleep debug functions in conditional compilation
* Remove erroneous changed
* Do not use CSS, remove it from everywhere
* Enable/disable USB on VBUS connect (prototype)
* FuriHal: add LPMS and DEEPSLEEP magic, workaround state inconsistency between cores
* FuriHal: honor c1 LMPS
* USB mode switch fix
* Applications: add flags and insomnia bypass system
* Correct spelling
* FuriHal: cleanup insomnia usage, reset sleep flags on wakeup, add shutdown api
* FuriHal: extra check on reinit request
* FuriHal: rename gpio_display_rst pin to gpio_display_rst_n
* FuriHal: add debug HAL
* FuriHal: add some magic to core2 reload procedure, fix issue with crash on ble keyboard exit
* FuriHal: cleanup ble glue, add BLE_GLUE_DEBUG flag
* FuriHal: ble reinit API, move os timer to LPTIM1 for deep sleep capability, shutdown that works
* FuriHal: take insomnia while shutdown
* Remove USB switch on/off on VBUS change
* Better tick skew handling
* Improve tick consistency under load
* Add USB_HP dummy IRQ handler
* Move interrupt check closer to sleep
* Clean up includes
* Re-enable Insomnia globally
* FuriHal: enable CSS
* FuriHal: remove questionable core2 clock shenanigans
* FuriHal: use core1 RCC registers in idle timer config
* FuriHal: return back CSS handlers, add lptim isr dispatching
Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
Co-authored-by: nminaylov <nm29719@gmail.com>
2022-04-29 16:29:51 +03:00
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furi_hal_power_insomnia_exit();
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2021-11-28 21:28:19 +03:00
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}
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2021-08-08 21:03:25 +03:00
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bool furi_hal_i2c_tx(
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2021-11-28 21:28:19 +03:00
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FuriHalI2cBusHandle* handle,
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2021-05-18 12:23:14 +03:00
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uint8_t address,
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const uint8_t* data,
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uint8_t size,
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uint32_t timeout) {
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2021-11-28 21:28:19 +03:00
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furi_check(handle->bus->current_handle == handle);
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2021-12-05 14:47:02 +03:00
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furi_assert(timeout > 0);
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2021-05-18 12:23:14 +03:00
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bool ret = true;
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2022-03-30 18:23:40 +03:00
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uint32_t timeout_tick = furi_hal_get_tick() + timeout;
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2021-05-18 12:23:14 +03:00
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2021-12-05 14:47:02 +03:00
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do {
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while(LL_I2C_IsActiveFlag_BUSY(handle->bus->i2c)) {
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2021-12-05 14:47:02 +03:00
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ret = false;
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break;
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}
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2021-05-18 12:23:14 +03:00
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}
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2021-12-05 14:47:02 +03:00
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if(!ret) {
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break;
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}
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LL_I2C_HandleTransfer(
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handle->bus->i2c,
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address,
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LL_I2C_ADDRSLAVE_7BIT,
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size,
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LL_I2C_MODE_AUTOEND,
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LL_I2C_GENERATE_START_WRITE);
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while(!LL_I2C_IsActiveFlag_STOP(handle->bus->i2c) || size > 0) {
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if(LL_I2C_IsActiveFlag_TXIS(handle->bus->i2c)) {
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LL_I2C_TransmitData8(handle->bus->i2c, (*data));
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data++;
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size--;
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}
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2021-05-18 12:23:14 +03:00
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ret = false;
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break;
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}
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}
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2021-12-05 14:47:02 +03:00
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LL_I2C_ClearFlag_STOP(handle->bus->i2c);
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} while(0);
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2021-05-18 12:23:14 +03:00
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return ret;
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}
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2021-08-08 21:03:25 +03:00
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bool furi_hal_i2c_rx(
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2021-11-28 21:28:19 +03:00
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FuriHalI2cBusHandle* handle,
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2021-05-18 12:23:14 +03:00
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uint8_t address,
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uint8_t* data,
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uint8_t size,
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uint32_t timeout) {
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2021-11-28 21:28:19 +03:00
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furi_check(handle->bus->current_handle == handle);
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2021-12-05 14:47:02 +03:00
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furi_assert(timeout > 0);
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2021-05-18 12:23:14 +03:00
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bool ret = true;
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2022-03-30 18:23:40 +03:00
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uint32_t timeout_tick = furi_hal_get_tick() + timeout;
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2021-12-05 14:47:02 +03:00
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do {
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while(LL_I2C_IsActiveFlag_BUSY(handle->bus->i2c)) {
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2021-12-05 14:47:02 +03:00
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ret = false;
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break;
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}
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}
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2021-05-18 12:23:14 +03:00
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2021-12-05 14:47:02 +03:00
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if(!ret) {
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break;
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2021-05-18 12:23:14 +03:00
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}
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2021-12-05 14:47:02 +03:00
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LL_I2C_HandleTransfer(
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handle->bus->i2c,
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address,
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LL_I2C_ADDRSLAVE_7BIT,
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size,
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LL_I2C_MODE_AUTOEND,
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LL_I2C_GENERATE_START_READ);
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while(!LL_I2C_IsActiveFlag_STOP(handle->bus->i2c) || size > 0) {
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if(LL_I2C_IsActiveFlag_RXNE(handle->bus->i2c)) {
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*data = LL_I2C_ReceiveData8(handle->bus->i2c);
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data++;
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size--;
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}
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2021-05-18 12:23:14 +03:00
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ret = false;
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break;
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}
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}
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2021-12-05 14:47:02 +03:00
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LL_I2C_ClearFlag_STOP(handle->bus->i2c);
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} while(0);
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2021-05-18 12:23:14 +03:00
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return ret;
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}
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2021-08-08 21:03:25 +03:00
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bool furi_hal_i2c_trx(
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2021-11-28 21:28:19 +03:00
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FuriHalI2cBusHandle* handle,
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2021-05-18 12:23:14 +03:00
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uint8_t address,
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const uint8_t* tx_data,
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uint8_t tx_size,
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uint8_t* rx_data,
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uint8_t rx_size,
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uint32_t timeout) {
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2021-11-28 21:28:19 +03:00
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if(furi_hal_i2c_tx(handle, address, tx_data, tx_size, timeout) &&
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furi_hal_i2c_rx(handle, address, rx_data, rx_size, timeout)) {
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2021-05-18 12:23:14 +03:00
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return true;
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} else {
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return false;
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}
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}
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2022-01-12 18:29:28 +03:00
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bool furi_hal_i2c_is_device_ready(FuriHalI2cBusHandle* handle, uint8_t i2c_addr, uint32_t timeout) {
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furi_check(handle);
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furi_check(handle->bus->current_handle == handle);
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furi_assert(timeout > 0);
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bool ret = true;
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2022-03-30 18:23:40 +03:00
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uint32_t timeout_tick = furi_hal_get_tick() + timeout;
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2022-01-12 18:29:28 +03:00
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do {
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while(LL_I2C_IsActiveFlag_BUSY(handle->bus->i2c)) {
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2022-01-12 18:29:28 +03:00
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return false;
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}
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}
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handle->bus->i2c->CR2 =
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((((uint32_t)(i2c_addr) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) &
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(~I2C_CR2_RD_WRN));
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while((!LL_I2C_IsActiveFlag_NACK(handle->bus->i2c)) &&
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(!LL_I2C_IsActiveFlag_STOP(handle->bus->i2c))) {
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2022-01-12 18:29:28 +03:00
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return false;
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}
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}
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if(LL_I2C_IsActiveFlag_NACK(handle->bus->i2c)) {
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while(!LL_I2C_IsActiveFlag_STOP(handle->bus->i2c)) {
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2022-01-12 18:29:28 +03:00
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return false;
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}
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}
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LL_I2C_ClearFlag_NACK(handle->bus->i2c);
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// Clear STOP Flag generated by autoend
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LL_I2C_ClearFlag_STOP(handle->bus->i2c);
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// Generate actual STOP
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LL_I2C_GenerateStopCondition(handle->bus->i2c);
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ret = false;
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}
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while(!LL_I2C_IsActiveFlag_STOP(handle->bus->i2c)) {
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2022-03-30 18:23:40 +03:00
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if(furi_hal_get_tick() >= timeout_tick) {
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2022-01-12 18:29:28 +03:00
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return false;
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}
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}
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LL_I2C_ClearFlag_STOP(handle->bus->i2c);
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} while(0);
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return ret;
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}
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bool furi_hal_i2c_read_reg_8(
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FuriHalI2cBusHandle* handle,
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uint8_t i2c_addr,
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uint8_t reg_addr,
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uint8_t* data,
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uint32_t timeout) {
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furi_check(handle);
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|
|
return furi_hal_i2c_trx(handle, i2c_addr, ®_addr, 1, data, 1, timeout);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool furi_hal_i2c_read_reg_16(
|
|
|
|
FuriHalI2cBusHandle* handle,
|
|
|
|
uint8_t i2c_addr,
|
|
|
|
uint8_t reg_addr,
|
|
|
|
uint16_t* data,
|
|
|
|
uint32_t timeout) {
|
|
|
|
furi_check(handle);
|
|
|
|
|
|
|
|
uint8_t reg_data[2];
|
|
|
|
bool ret = furi_hal_i2c_trx(handle, i2c_addr, ®_addr, 1, reg_data, 2, timeout);
|
|
|
|
*data = (reg_data[0] << 8) | (reg_data[1]);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool furi_hal_i2c_read_mem(
|
|
|
|
FuriHalI2cBusHandle* handle,
|
|
|
|
uint8_t i2c_addr,
|
|
|
|
uint8_t mem_addr,
|
|
|
|
uint8_t* data,
|
|
|
|
uint8_t len,
|
|
|
|
uint32_t timeout) {
|
|
|
|
furi_check(handle);
|
|
|
|
|
|
|
|
return furi_hal_i2c_trx(handle, i2c_addr, &mem_addr, 1, data, len, timeout);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool furi_hal_i2c_write_reg_8(
|
|
|
|
FuriHalI2cBusHandle* handle,
|
|
|
|
uint8_t i2c_addr,
|
|
|
|
uint8_t reg_addr,
|
|
|
|
uint8_t data,
|
|
|
|
uint32_t timeout) {
|
|
|
|
furi_check(handle);
|
|
|
|
|
|
|
|
uint8_t tx_data[2];
|
|
|
|
tx_data[0] = reg_addr;
|
|
|
|
tx_data[1] = data;
|
|
|
|
|
|
|
|
return furi_hal_i2c_tx(handle, i2c_addr, (const uint8_t*)&tx_data, 2, timeout);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool furi_hal_i2c_write_reg_16(
|
|
|
|
FuriHalI2cBusHandle* handle,
|
|
|
|
uint8_t i2c_addr,
|
|
|
|
uint8_t reg_addr,
|
|
|
|
uint16_t data,
|
|
|
|
uint32_t timeout) {
|
|
|
|
furi_check(handle);
|
|
|
|
|
|
|
|
uint8_t tx_data[3];
|
|
|
|
tx_data[0] = reg_addr;
|
|
|
|
tx_data[1] = (data >> 8) & 0xFF;
|
|
|
|
tx_data[2] = data & 0xFF;
|
|
|
|
|
|
|
|
return furi_hal_i2c_tx(handle, i2c_addr, (const uint8_t*)&tx_data, 3, timeout);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool furi_hal_i2c_write_mem(
|
|
|
|
FuriHalI2cBusHandle* handle,
|
|
|
|
uint8_t i2c_addr,
|
|
|
|
uint8_t mem_addr,
|
|
|
|
uint8_t* data,
|
|
|
|
uint8_t len,
|
|
|
|
uint32_t timeout) {
|
|
|
|
furi_check(handle);
|
|
|
|
|
|
|
|
furi_check(handle->bus->current_handle == handle);
|
|
|
|
furi_assert(timeout > 0);
|
|
|
|
|
|
|
|
bool ret = true;
|
|
|
|
uint8_t size = len + 1;
|
2022-03-30 18:23:40 +03:00
|
|
|
uint32_t timeout_tick = furi_hal_get_tick() + timeout;
|
2022-01-12 18:29:28 +03:00
|
|
|
|
|
|
|
do {
|
|
|
|
while(LL_I2C_IsActiveFlag_BUSY(handle->bus->i2c)) {
|
2022-03-30 18:23:40 +03:00
|
|
|
if(furi_hal_get_tick() >= timeout_tick) {
|
2022-01-12 18:29:28 +03:00
|
|
|
ret = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if(!ret) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
LL_I2C_HandleTransfer(
|
|
|
|
handle->bus->i2c,
|
|
|
|
i2c_addr,
|
|
|
|
LL_I2C_ADDRSLAVE_7BIT,
|
|
|
|
size,
|
|
|
|
LL_I2C_MODE_AUTOEND,
|
|
|
|
LL_I2C_GENERATE_START_WRITE);
|
|
|
|
|
|
|
|
while(!LL_I2C_IsActiveFlag_STOP(handle->bus->i2c) || size > 0) {
|
|
|
|
if(LL_I2C_IsActiveFlag_TXIS(handle->bus->i2c)) {
|
|
|
|
if(size == len + 1) {
|
|
|
|
LL_I2C_TransmitData8(handle->bus->i2c, mem_addr);
|
|
|
|
} else {
|
|
|
|
LL_I2C_TransmitData8(handle->bus->i2c, (*data));
|
|
|
|
data++;
|
|
|
|
}
|
|
|
|
size--;
|
|
|
|
}
|
|
|
|
|
2022-03-30 18:23:40 +03:00
|
|
|
if(furi_hal_get_tick() >= timeout_tick) {
|
2022-01-12 18:29:28 +03:00
|
|
|
ret = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
LL_I2C_ClearFlag_STOP(handle->bus->i2c);
|
|
|
|
} while(0);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|