2022-01-05 19:10:18 +03:00
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#include <furi_hal_uart.h>
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2021-10-26 21:41:56 +03:00
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#include <stdbool.h>
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#include <stm32wbxx_ll_lpuart.h>
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#include <stm32wbxx_ll_usart.h>
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2022-03-30 18:23:40 +03:00
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#include <stm32wbxx_ll_rcc.h>
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2022-01-05 19:10:18 +03:00
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#include <furi_hal_resources.h>
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2023-05-29 19:05:57 +03:00
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#include <furi_hal_bus.h>
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2021-10-26 21:41:56 +03:00
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#include <furi.h>
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[FL-2399, FL-2261] Tickless sleep shenanigans (#1168)
* Disable USART in sleep
* Restore UART state on suspend/resume
* FuriHal: Enable stop mode and add insomnia to I2C and SPI
* Remove IDLE interrupt
* FuriHal: add FPU isr and disable all FPU interrupt, add core2 stop mode configuration on deep sleep
* FuriHal: tie stop mode debug with debug rtc flag
* FuriHal: adjust flash latency on clock switch, tie mcu debug with RTC debug flag
* FuriHal: move resource init to early stage
* Add EXTI pending check, enable debug traps with compile-time flag
* Wrap sleep debug functions in conditional compilation
* Remove erroneous changed
* Do not use CSS, remove it from everywhere
* Enable/disable USB on VBUS connect (prototype)
* FuriHal: add LPMS and DEEPSLEEP magic, workaround state inconsistency between cores
* FuriHal: honor c1 LMPS
* USB mode switch fix
* Applications: add flags and insomnia bypass system
* Correct spelling
* FuriHal: cleanup insomnia usage, reset sleep flags on wakeup, add shutdown api
* FuriHal: extra check on reinit request
* FuriHal: rename gpio_display_rst pin to gpio_display_rst_n
* FuriHal: add debug HAL
* FuriHal: add some magic to core2 reload procedure, fix issue with crash on ble keyboard exit
* FuriHal: cleanup ble glue, add BLE_GLUE_DEBUG flag
* FuriHal: ble reinit API, move os timer to LPTIM1 for deep sleep capability, shutdown that works
* FuriHal: take insomnia while shutdown
* Remove USB switch on/off on VBUS change
* Better tick skew handling
* Improve tick consistency under load
* Add USB_HP dummy IRQ handler
* Move interrupt check closer to sleep
* Clean up includes
* Re-enable Insomnia globally
* FuriHal: enable CSS
* FuriHal: remove questionable core2 clock shenanigans
* FuriHal: use core1 RCC registers in idle timer config
* FuriHal: return back CSS handlers, add lptim isr dispatching
Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
Co-authored-by: nminaylov <nm29719@gmail.com>
2022-04-29 16:29:51 +03:00
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static bool furi_hal_usart_prev_enabled[2];
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2021-11-20 01:19:31 +03:00
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static void (*irq_cb[2])(uint8_t ev, uint8_t data, void* context);
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static void* irq_ctx[2];
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2021-10-26 21:41:56 +03:00
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static void furi_hal_usart_init(uint32_t baud) {
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2023-05-29 19:05:57 +03:00
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furi_hal_bus_enable(FuriHalBusUSART1);
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LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_PCLK2);
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2022-03-30 18:23:40 +03:00
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furi_hal_gpio_init_ex(
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2021-10-26 21:41:56 +03:00
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&gpio_usart_tx,
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GpioModeAltFunctionPushPull,
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GpioPullUp,
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GpioSpeedVeryHigh,
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GpioAltFn7USART1);
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2022-03-30 18:23:40 +03:00
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furi_hal_gpio_init_ex(
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2021-10-26 21:41:56 +03:00
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&gpio_usart_rx,
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GpioModeAltFunctionPushPull,
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GpioPullUp,
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GpioSpeedVeryHigh,
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GpioAltFn7USART1);
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2022-12-26 15:13:30 +03:00
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LL_USART_InitTypeDef USART_InitStruct;
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2021-10-26 21:41:56 +03:00
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USART_InitStruct.PrescalerValue = LL_USART_PRESCALER_DIV1;
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USART_InitStruct.BaudRate = baud;
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USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_8B;
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USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
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USART_InitStruct.Parity = LL_USART_PARITY_NONE;
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USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
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USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
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USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
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LL_USART_Init(USART1, &USART_InitStruct);
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LL_USART_EnableFIFO(USART1);
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LL_USART_ConfigAsyncMode(USART1);
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LL_USART_Enable(USART1);
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2022-02-10 14:20:50 +03:00
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while(!LL_USART_IsActiveFlag_TEACK(USART1) || !LL_USART_IsActiveFlag_REACK(USART1))
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2021-11-20 01:19:31 +03:00
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;
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2021-10-26 21:41:56 +03:00
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2023-03-22 17:41:14 +03:00
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LL_USART_DisableIT_ERROR(USART1);
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2022-03-30 18:23:40 +03:00
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NVIC_SetPriority(USART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
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2021-10-26 21:41:56 +03:00
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}
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static void furi_hal_lpuart_init(uint32_t baud) {
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2023-05-29 19:05:57 +03:00
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furi_hal_bus_enable(FuriHalBusLPUART1);
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LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1);
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2022-03-30 18:23:40 +03:00
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furi_hal_gpio_init_ex(
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2021-10-26 21:41:56 +03:00
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&gpio_ext_pc0,
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GpioModeAltFunctionPushPull,
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GpioPullUp,
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GpioSpeedVeryHigh,
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GpioAltFn8LPUART1);
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2022-03-30 18:23:40 +03:00
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furi_hal_gpio_init_ex(
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2021-10-26 21:41:56 +03:00
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&gpio_ext_pc1,
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GpioModeAltFunctionPushPull,
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GpioPullUp,
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GpioSpeedVeryHigh,
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GpioAltFn8LPUART1);
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2022-12-26 15:13:30 +03:00
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LL_LPUART_InitTypeDef LPUART_InitStruct;
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2021-10-26 21:41:56 +03:00
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LPUART_InitStruct.PrescalerValue = LL_LPUART_PRESCALER_DIV1;
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LPUART_InitStruct.BaudRate = 115200;
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LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B;
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LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1;
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LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE;
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LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
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LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
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LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
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LL_LPUART_EnableFIFO(LPUART1);
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LL_LPUART_Enable(LPUART1);
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2022-02-10 14:20:50 +03:00
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while(!LL_LPUART_IsActiveFlag_TEACK(LPUART1) || !LL_LPUART_IsActiveFlag_REACK(LPUART1))
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2021-11-20 01:19:31 +03:00
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;
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2021-10-26 21:41:56 +03:00
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furi_hal_uart_set_br(FuriHalUartIdLPUART1, baud);
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2023-03-22 17:41:14 +03:00
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LL_LPUART_DisableIT_ERROR(LPUART1);
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2021-10-26 21:41:56 +03:00
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2022-03-30 18:23:40 +03:00
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NVIC_SetPriority(LPUART1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
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2021-10-26 21:41:56 +03:00
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}
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void furi_hal_uart_init(FuriHalUartId ch, uint32_t baud) {
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2023-05-29 19:05:57 +03:00
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if(ch == FuriHalUartIdLPUART1) {
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2021-10-26 21:41:56 +03:00
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furi_hal_lpuart_init(baud);
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2023-05-29 19:05:57 +03:00
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} else if(ch == FuriHalUartIdUSART1) {
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2021-10-26 21:41:56 +03:00
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furi_hal_usart_init(baud);
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2023-05-29 19:05:57 +03:00
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}
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2021-10-26 21:41:56 +03:00
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}
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void furi_hal_uart_set_br(FuriHalUartId ch, uint32_t baud) {
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2021-11-20 01:19:31 +03:00
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if(ch == FuriHalUartIdUSART1) {
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if(LL_USART_IsEnabled(USART1)) {
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2021-10-26 21:41:56 +03:00
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// Wait for transfer complete flag
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2021-11-20 01:19:31 +03:00
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while(!LL_USART_IsActiveFlag_TC(USART1))
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;
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2021-10-26 21:41:56 +03:00
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LL_USART_Disable(USART1);
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uint32_t uartclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
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2021-11-20 01:19:31 +03:00
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LL_USART_SetBaudRate(
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USART1, uartclk, LL_USART_PRESCALER_DIV1, LL_USART_OVERSAMPLING_16, baud);
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2021-10-26 21:41:56 +03:00
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LL_USART_Enable(USART1);
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}
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2021-11-20 01:19:31 +03:00
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} else if(ch == FuriHalUartIdLPUART1) {
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if(LL_LPUART_IsEnabled(LPUART1)) {
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2021-10-26 21:41:56 +03:00
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// Wait for transfer complete flag
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2021-11-20 01:19:31 +03:00
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while(!LL_LPUART_IsActiveFlag_TC(LPUART1))
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;
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2021-10-26 21:41:56 +03:00
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LL_LPUART_Disable(LPUART1);
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2021-11-15 23:36:57 +03:00
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uint32_t uartclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
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2021-11-20 01:19:31 +03:00
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if(uartclk / baud > 4095) {
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2021-10-26 21:41:56 +03:00
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LL_LPUART_SetPrescaler(LPUART1, LL_LPUART_PRESCALER_DIV32);
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LL_LPUART_SetBaudRate(LPUART1, uartclk, LL_LPUART_PRESCALER_DIV32, baud);
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} else {
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LL_LPUART_SetPrescaler(LPUART1, LL_LPUART_PRESCALER_DIV1);
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LL_LPUART_SetBaudRate(LPUART1, uartclk, LL_LPUART_PRESCALER_DIV1, baud);
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}
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LL_LPUART_Enable(LPUART1);
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}
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}
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}
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void furi_hal_uart_deinit(FuriHalUartId ch) {
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2021-11-20 01:19:31 +03:00
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furi_hal_uart_set_irq_cb(ch, NULL, NULL);
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if(ch == FuriHalUartIdUSART1) {
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2023-05-29 19:05:57 +03:00
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if(furi_hal_bus_is_enabled(FuriHalBusUSART1)) {
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furi_hal_bus_disable(FuriHalBusUSART1);
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}
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2022-03-30 18:23:40 +03:00
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furi_hal_gpio_init(&gpio_usart_tx, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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furi_hal_gpio_init(&gpio_usart_rx, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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2021-11-20 01:19:31 +03:00
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} else if(ch == FuriHalUartIdLPUART1) {
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2023-05-29 19:05:57 +03:00
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if(furi_hal_bus_is_enabled(FuriHalBusLPUART1)) {
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furi_hal_bus_disable(FuriHalBusLPUART1);
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}
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2022-03-30 18:23:40 +03:00
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furi_hal_gpio_init(&gpio_ext_pc0, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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furi_hal_gpio_init(&gpio_ext_pc1, GpioModeAnalog, GpioPullNo, GpioSpeedLow);
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2021-10-26 21:41:56 +03:00
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}
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}
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[FL-2399, FL-2261] Tickless sleep shenanigans (#1168)
* Disable USART in sleep
* Restore UART state on suspend/resume
* FuriHal: Enable stop mode and add insomnia to I2C and SPI
* Remove IDLE interrupt
* FuriHal: add FPU isr and disable all FPU interrupt, add core2 stop mode configuration on deep sleep
* FuriHal: tie stop mode debug with debug rtc flag
* FuriHal: adjust flash latency on clock switch, tie mcu debug with RTC debug flag
* FuriHal: move resource init to early stage
* Add EXTI pending check, enable debug traps with compile-time flag
* Wrap sleep debug functions in conditional compilation
* Remove erroneous changed
* Do not use CSS, remove it from everywhere
* Enable/disable USB on VBUS connect (prototype)
* FuriHal: add LPMS and DEEPSLEEP magic, workaround state inconsistency between cores
* FuriHal: honor c1 LMPS
* USB mode switch fix
* Applications: add flags and insomnia bypass system
* Correct spelling
* FuriHal: cleanup insomnia usage, reset sleep flags on wakeup, add shutdown api
* FuriHal: extra check on reinit request
* FuriHal: rename gpio_display_rst pin to gpio_display_rst_n
* FuriHal: add debug HAL
* FuriHal: add some magic to core2 reload procedure, fix issue with crash on ble keyboard exit
* FuriHal: cleanup ble glue, add BLE_GLUE_DEBUG flag
* FuriHal: ble reinit API, move os timer to LPTIM1 for deep sleep capability, shutdown that works
* FuriHal: take insomnia while shutdown
* Remove USB switch on/off on VBUS change
* Better tick skew handling
* Improve tick consistency under load
* Add USB_HP dummy IRQ handler
* Move interrupt check closer to sleep
* Clean up includes
* Re-enable Insomnia globally
* FuriHal: enable CSS
* FuriHal: remove questionable core2 clock shenanigans
* FuriHal: use core1 RCC registers in idle timer config
* FuriHal: return back CSS handlers, add lptim isr dispatching
Co-authored-by: Aleksandr Kutuzov <alleteam@gmail.com>
Co-authored-by: nminaylov <nm29719@gmail.com>
2022-04-29 16:29:51 +03:00
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void furi_hal_uart_suspend(FuriHalUartId channel) {
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if(channel == FuriHalUartIdLPUART1 && LL_LPUART_IsEnabled(LPUART1)) {
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LL_LPUART_Disable(LPUART1);
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furi_hal_usart_prev_enabled[channel] = true;
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} else if(channel == FuriHalUartIdUSART1 && LL_USART_IsEnabled(USART1)) {
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LL_USART_Disable(USART1);
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furi_hal_usart_prev_enabled[channel] = true;
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}
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}
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void furi_hal_uart_resume(FuriHalUartId channel) {
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if(!furi_hal_usart_prev_enabled[channel]) {
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return;
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} else if(channel == FuriHalUartIdLPUART1) {
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LL_LPUART_Enable(LPUART1);
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} else if(channel == FuriHalUartIdUSART1) {
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LL_USART_Enable(USART1);
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}
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furi_hal_usart_prev_enabled[channel] = false;
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}
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2021-10-26 21:41:56 +03:00
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void furi_hal_uart_tx(FuriHalUartId ch, uint8_t* buffer, size_t buffer_size) {
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2021-11-20 01:19:31 +03:00
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if(ch == FuriHalUartIdUSART1) {
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if(LL_USART_IsEnabled(USART1) == 0) return;
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2021-10-26 21:41:56 +03:00
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while(buffer_size > 0) {
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2021-11-20 01:19:31 +03:00
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while(!LL_USART_IsActiveFlag_TXE(USART1))
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;
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2021-10-26 21:41:56 +03:00
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LL_USART_TransmitData8(USART1, *buffer);
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buffer++;
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buffer_size--;
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}
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2021-11-20 01:19:31 +03:00
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} else if(ch == FuriHalUartIdLPUART1) {
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if(LL_LPUART_IsEnabled(LPUART1) == 0) return;
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2021-10-26 21:41:56 +03:00
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while(buffer_size > 0) {
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2021-11-20 01:19:31 +03:00
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while(!LL_LPUART_IsActiveFlag_TXE(LPUART1))
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;
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2021-10-26 21:41:56 +03:00
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LL_LPUART_TransmitData8(LPUART1, *buffer);
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2021-11-20 01:19:31 +03:00
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2021-10-26 21:41:56 +03:00
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buffer++;
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buffer_size--;
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}
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}
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}
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2021-11-20 01:19:31 +03:00
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void furi_hal_uart_set_irq_cb(
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FuriHalUartId ch,
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void (*cb)(UartIrqEvent ev, uint8_t data, void* ctx),
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void* ctx) {
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if(cb == NULL) {
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2023-03-22 17:41:14 +03:00
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if(ch == FuriHalUartIdUSART1) {
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2021-10-26 21:41:56 +03:00
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NVIC_DisableIRQ(USART1_IRQn);
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2023-03-22 17:41:14 +03:00
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LL_USART_DisableIT_RXNE_RXFNE(USART1);
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} else if(ch == FuriHalUartIdLPUART1) {
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2021-10-26 21:41:56 +03:00
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NVIC_DisableIRQ(LPUART1_IRQn);
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2023-03-22 17:41:14 +03:00
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LL_LPUART_DisableIT_RXNE_RXFNE(LPUART1);
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}
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2021-10-26 21:41:56 +03:00
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irq_cb[ch] = cb;
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2021-11-20 01:19:31 +03:00
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irq_ctx[ch] = ctx;
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2021-10-26 21:41:56 +03:00
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} else {
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2021-11-20 01:19:31 +03:00
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irq_ctx[ch] = ctx;
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2021-10-26 21:41:56 +03:00
|
|
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irq_cb[ch] = cb;
|
2023-03-22 17:41:14 +03:00
|
|
|
if(ch == FuriHalUartIdUSART1) {
|
2021-10-26 21:41:56 +03:00
|
|
|
NVIC_EnableIRQ(USART1_IRQn);
|
2023-03-22 17:41:14 +03:00
|
|
|
LL_USART_EnableIT_RXNE_RXFNE(USART1);
|
|
|
|
} else if(ch == FuriHalUartIdLPUART1) {
|
2021-10-26 21:41:56 +03:00
|
|
|
NVIC_EnableIRQ(LPUART1_IRQn);
|
2023-03-22 17:41:14 +03:00
|
|
|
LL_LPUART_EnableIT_RXNE_RXFNE(LPUART1);
|
|
|
|
}
|
2021-10-26 21:41:56 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void LPUART1_IRQHandler(void) {
|
2021-11-20 01:19:31 +03:00
|
|
|
if(LL_LPUART_IsActiveFlag_RXNE_RXFNE(LPUART1)) {
|
2021-10-26 21:41:56 +03:00
|
|
|
uint8_t data = LL_LPUART_ReceiveData8(LPUART1);
|
2021-11-20 01:19:31 +03:00
|
|
|
irq_cb[FuriHalUartIdLPUART1](UartIrqEventRXNE, data, irq_ctx[FuriHalUartIdLPUART1]);
|
|
|
|
} else if(LL_LPUART_IsActiveFlag_ORE(LPUART1)) {
|
2021-11-04 22:33:28 +03:00
|
|
|
LL_LPUART_ClearFlag_ORE(LPUART1);
|
2021-10-26 21:41:56 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void USART1_IRQHandler(void) {
|
2021-11-20 01:19:31 +03:00
|
|
|
if(LL_USART_IsActiveFlag_RXNE_RXFNE(USART1)) {
|
2021-10-26 21:41:56 +03:00
|
|
|
uint8_t data = LL_USART_ReceiveData8(USART1);
|
2021-11-20 01:19:31 +03:00
|
|
|
irq_cb[FuriHalUartIdUSART1](UartIrqEventRXNE, data, irq_ctx[FuriHalUartIdUSART1]);
|
|
|
|
} else if(LL_USART_IsActiveFlag_ORE(USART1)) {
|
2021-11-04 22:33:28 +03:00
|
|
|
LL_USART_ClearFlag_ORE(USART1);
|
2021-10-26 21:41:56 +03:00
|
|
|
}
|
|
|
|
}
|