<?xml version="1.0" encoding="UTF-8"?><device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd"><name>STM32WB55_CM4</name><version>1.9</version><description>STM32WB55_CM4</description><cpu><name>CM4</name><revision>r0p1</revision><endian>little</endian><mpuPresent>true</mpuPresent><fpuPresent>true</fpuPresent><nvicPrioBits>4</nvicPrioBits><vendorSystickConfig>false</vendorSystickConfig></cpu><addressUnitBits>8</addressUnitBits><width>32</width><size>0x20</size><resetValue>0x0</resetValue><resetMask>0xFFFFFFFF</resetMask><peripherals><peripheral><name>DMA1</name><description>Direct memory access controller</description><groupName>DMA</groupName><baseAddress>0x40020000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>DMA1_Channel1</name><description>DMA1 Channel1 global interrupt</description><value>11</value></interrupt><interrupt><name>DMA1_Channel2</name><description>DMA1 Channel2 global interrupt</description><value>12</value></interrupt><interrupt><name>DMA1_Channel3</name><description>DMA1 Channel3 interrupt</description><value>13</value></interrupt><interrupt><name>DMA1_Channel4</name><description>DMA1 Channel4 interrupt</description><value>14</value></interrupt><interrupt><name>DMA1_Channel5</name><description>DMA1 Channel5 interrupt</description><value>15</value></interrupt><interrupt><name>DMA1_Channel6</name><description>DMA1 Channel6 interrupt</description><value>16</value></interrupt><interrupt><name>DMA1_Channel7</name><description>DMA1 Channel 7 interrupt</description><value>17</value></interrupt><registers><register><name>ISR</name><displayName>ISR</displayName><description>interrupt status register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>TEIF7</name><description>Channel x transfer error flag (x = 1 ..7)</description><bitOffset>27</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF7</name><description>Channel x half transfer flag (x = 1 ..7)</description><bitOffset>26</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF7</name><description>Channel x transfer complete flag (x = 1 ..7)</description><bitOffset>25</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF7</name><description>Channel x global interrupt flag (x = 1 ..7)</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF6</name><description>Channel x transfer error flag (x = 1 ..7)</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF6</name><description>Channel x half transfer flag (x = 1 ..7)</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF6</name><description>Channel x transfer complete flag (x = 1 ..7)</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF6</name><description>Channel x global interrupt flag (x = 1 ..7)</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF5</name><description>Channel x transfer error flag (x = 1 ..7)</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF5</name><description>Channel x half transfer flag (x = 1 ..7)</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>TCIF5</name><description>Channel x transfer complete flag (x = 1 ..7)</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>GIF5</name><description>Channel x global interrupt flag (x = 1 ..7)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>TEIF4</name><description>Channel x transfer error flag (x = 1 ..7)</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>HTIF4</name><description>Channel x half tr
interrupt</description><value>43</value></interrupt><registers><register><name>CR1</name><displayName>CR1</displayName><description>Power control register 1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000200</resetValue><fields><field><name>LPR</name><description>Low-power run</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>VOS</name><description>Voltage scaling range selection</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>DBP</name><description>Disable backup domain write protection</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>FPDS</name><description>Flash power down mode during LPsSleep for CPU1</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>FPDR</name><description>Flash power down mode during LPRun for CPU1</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>LPMS</name><description>Low-power mode selection for CPU1</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>Power control register 2</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>USV</name><description>VDDUSB USB supply valid</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>PVME3</name><description>Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>PVME1</name><description>Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>PLS</name><description>Power voltage detector level selection</description><bitOffset>1</bitOffset><bitWidth>3</bitWidth></field><field><name>PVDE</name><description>Power voltage detector enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR3</name><displayName>CR3</displayName><description>Power control register 3</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00008000</resetValue><fields><field><name>EIWUL</name><description>Enable internal wakeup line for CPU1</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field><field><name>EC2H</name><description>Enable CPU2 Hold interrupt for CPU1</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>E802A</name><description>Enable end of activity interrupt for CPU1</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>EBLEA</name><description>Enable BLE end of activity interrupt for CPU1</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ECRPE</name><description>Enable critical radio phase end of activity interrupt for CPU1</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>APC</name><description>Apply pull-up and pull-down configuration</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>RRS</name><description>SRAM2a retention in Standby mode</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>EBORHSDFB</name><description>Enable BORH and Step Down counverter forced in Bypass interrups for CPU1</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EWUP5</name><description>Enable Wakeup pin WKUP5</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>EWUP4</name><description>Enable Wakeup pin WKUP4</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>EWUP3</name><desc
AIEC[21:20]</description><value>22</value></interrupt><registers><register><name>COMP1_CSR</name><displayName>COMP1_CSR</displayName><description>Comparator control and status register</description><addressOffset>0x0</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>COMP1_EN</name><description>Comparator enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>COMP1_PWRMODE</name><description>Comparator power mode</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP1_INMSEL</name><description>Comparator input minus selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>COMP1_INPSEL</name><description>Comparator input plus selection</description><bitOffset>7</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP1_POLARITY</name><description>Comparator output polarity</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>COMP1_HYST</name><description>Comparator hysteresis</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP1_BLANKING</name><description>Comparator blanking source</description><bitOffset>18</bitOffset><bitWidth>3</bitWidth><access>read-write</access></field><field><name>COMP1_BRGEN</name><description>Comparator voltage scaler enable</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>COMP1_SCALEN</name><description>Comparator scaler bridge enable</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>COMP1_INMESEL</name><description>Comparator input minus extended selection</description><bitOffset>25</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP1_VALUE</name><description>Comparator output level</description><bitOffset>30</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>COMP1_LOCK</name><description>Comparator lock</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field></fields></register><register><name>COMP2_CSR</name><displayName>COMP2_CSR</displayName><description>Comparator 2 control and status register</description><addressOffset>0x4</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>COMP2_EN</name><description>Comparator 2 enable bit</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>COMP2_PWRMODE</name><description>Power Mode of the comparator 2</description><bitOffset>2</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP2_INMSEL</name><description>Comparator 2 input minus selection bits</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP2_INPSEL</name><description>Comparator 1 input plus selection bit</description><bitOffset>7</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP2_WINMODE</name><description>Windows mode selection bit</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>COMP2_POLARITY</name><description>Comparator 2 polarity selection bit</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>COMP2_HYST</name><description>Comparator 2 hysteresis selection bits</description><bitOffset>16</bitOffset><bitWidth>2</bitWidth><access>read-write</access></field><field><name>COMP2_BLANKING</name><description>Comparator 2 blanking source selection bits</description><bitOffset>18</bitOffset><bitWidth>3</bitWidth><access>read-w
interrupt</description><value>53</value></interrupt><registers><register><name>CR</name><displayName>CR</displayName><description>control register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>RNGEN</name><description>Random number generator enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>IE</name><description>Interrupt enable</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>BYP</name><description>Bypass mode enable</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>status register</description><addressOffset>0x4</addressOffset><size>0x20</size><resetValue>0x00000000</resetValue><fields><field><name>SEIS</name><description>Seed error interrupt status</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>CEIS</name><description>Clock error interrupt status</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth><access>read-write</access></field><field><name>SECS</name><description>Seed error current status</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>CECS</name><description>Clock error current status</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field><field><name>DRDY</name><description>Data ready</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth><access>read-only</access></field></fields></register><register><name>DR</name><displayName>DR</displayName><description>data register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>RNDATA</name><description>Random data</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register></registers></peripheral><peripheral><name>AES1</name><description>Advanced encryption standard hardware accelerator 1</description><groupName>AES1</groupName><baseAddress>0x50060000</baseAddress><addressBlock><offset>0x0</offset><size>0x400</size><usage>registers</usage></addressBlock><interrupt><name>AES1</name><description>AES1 global interrupt</description><value>51</value></interrupt><registers><register><name>CR</name><displayName>CR</displayName><description>control register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>NPBLB</name><description>Number of padding bytes in last block of payload</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>KEYSIZE</name><description>Key size selection</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>CHMOD2</name><description>AES chaining mode Bit2</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>GCMPH</name><description>Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected</description><bitOffset>13</bitOffset><bitWidth>2</bitWidth></field><field><name>DMAOUTEN</name><description>Enable DMA management of data output phase</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>DMAINEN</name><description>Enable DMA management of data input phase</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ERRIE</name><description>Error interrupt enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>CCFIE</name><description>CCF flag interrupt enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>ERRC</name><description>Error clear</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>CCFC</name><description>Compu
TIM17 global interrupt</description><value>26</value></interrupt><interrupt><name>TIM1_CC</name><description>TIM1 Capture Compare interrupt</description><value>27</value></interrupt><registers><register><name>CR1</name><displayName>CR1</displayName><description>control register 1</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>CEN</name><description>Counter enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field><field><name>OPM</name><description>One-pulse mode</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>UDIS</name><description>Update disable</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>URS</name><description>Update request source</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>DIR</name><description>Direction</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>CMS</name><description>Center-aligned mode selection</description><bitOffset>5</bitOffset><bitWidth>2</bitWidth></field><field><name>ARPE</name><description>Auto-reload preload enable</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>CKD</name><description>Clock division</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field><field><name>UIFREMAP</name><description>UIF status bit remapping</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CR2</name><displayName>CR2</displayName><description>control register 2</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>MMS2</name><description>Master mode selection 2</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>OIS6</name><description>Output Idle state 6 (OC6 output)</description><bitOffset>18</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS5</name><description>Output Idle state 5 (OC5 output)</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS4</name><description>Output Idle state 4</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS3N</name><description>Output Idle state 3</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS3</name><description>Output Idle state 3</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS2N</name><description>Output Idle state 2</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS2</name><description>Output Idle state 2</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS1N</name><description>Output Idle state 1</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>OIS1</name><description>Output Idle state 1</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>TI1S</name><description>TI1 selection</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>MMS</name><description>Master mode selection</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>CCDS</name><description>Capture/compare DMA selection</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>CCUS</name><description>Capture/compare control update selection</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>CCPC</name><description>Capture/compare preloaded control</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SMCR</name><displayName>SMCR</displayName><description>slave mode control register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x0000</resetValue><fields><field><name>SMS</name><description>Slave mode selectio
AIEC</description><value>41</value></interrupt><registers><register><name>TR</name><displayName>TR</displayName><description>time register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PM</name><description>AM/PM notation</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field><field><name>HT</name><description>Hour tens in BCD format</description><bitOffset>20</bitOffset><bitWidth>2</bitWidth></field><field><name>HU</name><description>Hour units in BCD format</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>MNT</name><description>Minute tens in BCD format</description><bitOffset>12</bitOffset><bitWidth>3</bitWidth></field><field><name>MNU</name><description>Minute units in BCD format</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>ST</name><description>Second tens in BCD format</description><bitOffset>4</bitOffset><bitWidth>3</bitWidth></field><field><name>SU</name><description>Second units in BCD format</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>DR</name><displayName>DR</displayName><description>date register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00002101</resetValue><fields><field><name>YT</name><description>Year tens in BCD format</description><bitOffset>20</bitOffset><bitWidth>4</bitWidth></field><field><name>YU</name><description>Year units in BCD format</description><bitOffset>16</bitOffset><bitWidth>4</bitWidth></field><field><name>WDU</name><description>Week day units</description><bitOffset>13</bitOffset><bitWidth>3</bitWidth></field><field><name>MT</name><description>Month tens in BCD format</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>MU</name><description>Month units in BCD format</description><bitOffset>8</bitOffset><bitWidth>4</bitWidth></field><field><name>DT</name><description>Date tens in BCD format</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DU</name><description>Date units in BCD format</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>CR</name><displayName>CR</displayName><description>control register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>WCKSEL</name><description>Wakeup clock selection</description><bitOffset>0</bitOffset><bitWidth>3</bitWidth></field><field><name>TSEDGE</name><description>Time-stamp event active edge</description><bitOffset>3</bitOffset><bitWidth>1</bitWidth></field><field><name>REFCKON</name><description>Reference clock detection enable (50 or 60 Hz)</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field><field><name>BYPSHAD</name><description>Bypass the shadow registers</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field><field><name>FMT</name><description>Hour format</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRAE</name><description>Alarm A enable</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRBE</name><description>Alarm B enable</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field><field><name>WUTE</name><description>Wakeup timer enable</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field><field><name>TSE</name><description>Time stamp enable</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRAIE</name><description>Alarm A interrupt enable</description><bitOffset>12</bitOffset><bitWidth>1</bitWidth></field><field><name>ALRBIE</name><description>Alarm B interrupt enable</description><bitOffset>13</bitOffset><bitWidth>1</bitWidth></field><field><name>WUTIE</name><description>Wakeup timer interrupt enable</description><bitOffset>1
interrupt</description><value>29</value></interrupt><registers><register><name>CR</name><displayName>CR</displayName><description>Control register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ADDRERRIE</name><description>Address error interrupt enable</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>RAMERRIE</name><description>RAM error interrupt enable</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>PROCENDIE</name><description>End of operation interrupt enable</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>MODE</name><description>PKA Operation Mode</description><bitOffset>8</bitOffset><bitWidth>6</bitWidth></field><field><name>SECLVL</name><description>Security Enable</description><bitOffset>2</bitOffset><bitWidth>1</bitWidth></field><field><name>START</name><description>Start the operation</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>EN</name><description>Peripheral Enable</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SR</name><displayName>SR</displayName><description>PKA status register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000000</resetValue><fields><field><name>ADDRERRF</name><description>Address error flag</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>RAMERRF</name><description>RAM error flag</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>PROCENDF</name><description>PKA End of Operation flag</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field><field><name>BUSY</name><description>PKA Operation in progress</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>CLRFR</name><displayName>CLRFR</displayName><description>PKA clear flag register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>ADDRERRFC</name><description>Clear Address error flag</description><bitOffset>20</bitOffset><bitWidth>1</bitWidth></field><field><name>RAMERRFC</name><description>Clear RAM error flag</description><bitOffset>19</bitOffset><bitWidth>1</bitWidth></field><field><name>PROCENDFC</name><description>Clear PKA End of Operation flag</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>VERR</name><displayName>VERR</displayName><description>PKA version register</description><addressOffset>0x1FF4</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00000010</resetValue><fields><field><name>MINREV</name><description>Minor revision</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>MAJREV</name><description>Major revision</description><bitOffset>4</bitOffset><bitWidth>4</bitWidth></field></fields></register><register><name>IPIDR</name><displayName>IPIDR</displayName><description>PKA identification register</description><addressOffset>0x1FF8</addressOffset><size>0x20</size><access>read-only</access><resetValue>0x00170061</resetValue><fields><field><name>ID</name><description>Identification Code</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register><register><name>SIDR</name><displayName>SIDR</displayName><description>PKA size ID register</description><addressOffset>0x1FFC</addressOffset><size>0x20</size><access>read-only</access><resetValue>0xA3C5DD08</resetValue><fields><field><name>SID</name><description>Side Identification Code</description><bitOffset>0</bitOffset><bitWidth>32</bitWidth></field></fields></register></registers></peripheral><peripheral><name>IPCC</name><description>IPCC</description><groupName>IPCC</groupName><baseAddress>0x58000C00</baseAddress><addressBlock><offset>
EXTI[0]</description><value>6</value></interrupt><interrupt><name>EXTI1</name><description>EXTI line 0 interrupt through
EXTI[1]</description><value>7</value></interrupt><interrupt><name>EXTI2</name><description>EXTI line 0 interrupt through
EXTI[2]</description><value>8</value></interrupt><interrupt><name>EXTI3</name><description>EXTI line 0 interrupt through
EXTI[3]</description><value>9</value></interrupt><interrupt><name>EXTI4</name><description>EXTI line 0 interrupt through
EXTI[4]</description><value>10</value></interrupt><interrupt><name>C2SEV</name><description>CPU2 SEV through EXTI[40]</description><value>21</value></interrupt><interrupt><name>EXTI5_9</name><description>EXTI line [9:5] interrupt through
EXTI[9:5]</description><value>23</value></interrupt><interrupt><name>EXTI10_15</name><description>EXTI line [15:10] interrupt through
EXTI[15:10]</description><value>40</value></interrupt><registers><register><name>RTSR1</name><displayName>RTSR1</displayName><description>rising trigger selection register</description><addressOffset>0x0</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>RT</name><description>Rising trigger event configuration bit of Configurable Event input</description><bitOffset>0</bitOffset><bitWidth>22</bitWidth></field><field><name>RT_31</name><description>Rising trigger event configuration bit of Configurable Event input</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>FTSR1</name><displayName>FTSR1</displayName><description>falling trigger selection register</description><addressOffset>0x4</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>FT</name><description>Falling trigger event configuration bit of Configurable Event input</description><bitOffset>0</bitOffset><bitWidth>22</bitWidth></field><field><name>FT_31</name><description>Falling trigger event configuration bit of Configurable Event input</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>SWIER1</name><displayName>SWIER1</displayName><description>software interrupt event register</description><addressOffset>0x8</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SWI</name><description>Software interrupt on event</description><bitOffset>0</bitOffset><bitWidth>22</bitWidth></field><field><name>SWI_31</name><description>Software interrupt on event</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>PR1</name><displayName>PR1</displayName><description>EXTI pending register</description><addressOffset>0xC</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>PIF</name><description>Configurable event inputs Pending bit</description><bitOffset>0</bitOffset><bitWidth>22</bitWidth></field><field><name>PIF_31</name><description>Configurable event inputs Pending bit</description><bitOffset>31</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>RTSR2</name><displayName>RTSR2</displayName><description>rising trigger selection register</description><addressOffset>0x20</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>RT33</name><description>Rising trigger event configuration bit of Configurable Event input</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>RT40_41</name><description>Rising trigger event configuration bit of Configurable Event input</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>FTSR2</name><displayName>FTSR2</displayName><description>falling trigger selection register</description><addressOffset>0x24</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>FT33</name><description>Falling trigger event configuration bit of Configurable Event input</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field><field><name>FT40_41</name><description>Falling trigger event configuration bit of Configurable Event input</description><bitOffset>8</bitOffset><bitWidth>2</bitWidth></field></fields></register><register><name>SWIER2</name><displayName>SWIER2</displayName><description>software interrupt event register</description><addressOffset>0x28</addressOffset><size>0x20</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>SWI33</name><description>Software interrupt on
wakeup)</description><value>20</value></interrupt><registers><register><name>EP0R</name><displayName>EP0R</displayName><description>endpoint 0 register</description><addressOffset>0x0</addressOffset><size>0x10</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>EP1R</name><displayName>EP1R</displayName><description>endpoint 1 register</description><addressOffset>0x4</addressOffset><size>0x10</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission transfers</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_TX</name><description>Correct Transfer for transmission</description><bitOffset>7</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_KIND</name><description>Endpoint kind</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field><field><name>EP_TYPE</name><description>Endpoint type</description><bitOffset>9</bitOffset><bitWidth>2</bitWidth></field><field><name>SETUP</name><description>Setup transaction completed</description><bitOffset>11</bitOffset><bitWidth>1</bitWidth></field><field><name>STAT_RX</name><description>Status bits, for reception transfers</description><bitOffset>12</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_RX</name><description>Data Toggle, for reception transfers</description><bitOffset>14</bitOffset><bitWidth>1</bitWidth></field><field><name>CTR_RX</name><description>Correct transfer for reception</description><bitOffset>15</bitOffset><bitWidth>1</bitWidth></field></fields></register><register><name>EP2R</name><displayName>EP2R</displayName><description>endpoint 2 register</description><addressOffset>0x8</addressOffset><size>0x10</size><access>read-write</access><resetValue>0x00000000</resetValue><fields><field><name>EA</name><description>Endpoint address</description><bitOffset>0</bitOffset><bitWidth>4</bitWidth></field><field><name>STAT_TX</name><description>Status bits, for transmission transfers</description><bitOffset>4</bitOffset><bitWidth>2</bitWidth></field><field><name>DTOG_TX</name><description>Data Toggle, for transmission transfers</description><bitOffset>6</
