diff --git a/SConstruct b/SConstruct index 44ee77467..36e060023 100644 --- a/SConstruct +++ b/SConstruct @@ -77,6 +77,8 @@ if GetOption("fullenv") or any( "${COPRO_DISCLAIMER}", "--obdata", '"${ROOT_DIR.abspath}/${COPRO_OB_DATA}"', + "--stackversion", + "${COPRO_CUBE_VERSION}", ] dist_resource_arguments = [ "-r", diff --git a/fbt_options.py b/fbt_options.py index bd804fc8b..d13abbe5e 100644 --- a/fbt_options.py +++ b/fbt_options.py @@ -22,7 +22,7 @@ DIST_SUFFIX = "local" COPRO_OB_DATA = "scripts/ob.data" # Must match lib/stm32wb_copro version -COPRO_CUBE_VERSION = "1.15.0" +COPRO_CUBE_VERSION = "1.17.2" COPRO_CUBE_DIR = "lib/stm32wb_copro" diff --git a/firmware/targets/f18/api_symbols.csv b/firmware/targets/f18/api_symbols.csv index 0c2064931..bc17ff2fa 100644 --- a/firmware/targets/f18/api_symbols.csv +++ b/firmware/targets/f18/api_symbols.csv @@ -1020,8 +1020,10 @@ Function,+,furi_hal_clock_mco_disable,void, Function,+,furi_hal_clock_mco_enable,void,"FuriHalClockMcoSourceId, FuriHalClockMcoDivisorId" Function,-,furi_hal_clock_resume_tick,void, Function,-,furi_hal_clock_suspend_tick,void, -Function,-,furi_hal_clock_switch_to_hsi,void, -Function,-,furi_hal_clock_switch_to_pll,void, +Function,-,furi_hal_clock_switch_hse2hsi,void, +Function,-,furi_hal_clock_switch_hse2pll,_Bool, +Function,-,furi_hal_clock_switch_hsi2hse,void, +Function,-,furi_hal_clock_switch_pll2hse,_Bool, Function,+,furi_hal_console_disable,void, Function,+,furi_hal_console_enable,void, Function,+,furi_hal_console_init,void, diff --git a/firmware/targets/f7/api_symbols.csv b/firmware/targets/f7/api_symbols.csv index 081985154..26fad6b58 100644 --- a/firmware/targets/f7/api_symbols.csv +++ b/firmware/targets/f7/api_symbols.csv @@ -1091,8 +1091,10 @@ Function,+,furi_hal_clock_mco_disable,void, Function,+,furi_hal_clock_mco_enable,void,"FuriHalClockMcoSourceId, FuriHalClockMcoDivisorId" Function,-,furi_hal_clock_resume_tick,void, Function,-,furi_hal_clock_suspend_tick,void, -Function,-,furi_hal_clock_switch_to_hsi,void, -Function,-,furi_hal_clock_switch_to_pll,void, +Function,-,furi_hal_clock_switch_hse2hsi,void, +Function,-,furi_hal_clock_switch_hse2pll,_Bool, +Function,-,furi_hal_clock_switch_hsi2hse,void, +Function,-,furi_hal_clock_switch_pll2hse,_Bool, Function,+,furi_hal_console_disable,void, Function,+,furi_hal_console_enable,void, Function,+,furi_hal_console_init,void, diff --git a/firmware/targets/f7/ble_glue/app_common.h b/firmware/targets/f7/ble_glue/app_common.h index 8eaf23085..e969636d2 100644 --- a/firmware/targets/f7/ble_glue/app_common.h +++ b/firmware/targets/f7/ble_glue/app_common.h @@ -1,30 +1,4 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : app_common.h - * Description : App Common application configuration file for STM32WPAN Middleware. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef APP_COMMON_H -#define APP_COMMON_H - -#ifdef __cplusplus -extern "C" { -#endif +#pragma once #include #include @@ -36,5 +10,3 @@ extern "C" { #include #include "app_conf.h" - -#endif diff --git a/firmware/targets/f7/ble_glue/app_conf.h b/firmware/targets/f7/ble_glue/app_conf.h index ee5115cfe..25fa688c7 100644 --- a/firmware/targets/f7/ble_glue/app_conf.h +++ b/firmware/targets/f7/ble_glue/app_conf.h @@ -1,80 +1,32 @@ #pragma once -#include "hw_conf.h" -#include "hw_if.h" - -#include -#include +#include #define CFG_TX_POWER (0x19) /* +0dBm */ #define CFG_IDENTITY_ADDRESS GAP_PUBLIC_ADDR -/** - * Define Advertising parameters - */ -#define CFG_ADV_BD_ADDRESS (0x7257acd87a6c) -#define CFG_FAST_CONN_ADV_INTERVAL_MIN (0x80) /**< 80ms */ -#define CFG_FAST_CONN_ADV_INTERVAL_MAX (0xa0) /**< 100ms */ -#define CFG_LP_CONN_ADV_INTERVAL_MIN (0x640) /**< 1s */ -#define CFG_LP_CONN_ADV_INTERVAL_MAX (0xfa0) /**< 2.5s */ - /** * Define IO Authentication */ -#define CFG_BONDING_MODE (1) -#define CFG_FIXED_PIN (111111) -#define CFG_USED_FIXED_PIN (1) +#define CFG_USED_FIXED_PIN USE_FIXED_PIN_FOR_PAIRING_FORBIDDEN #define CFG_ENCRYPTION_KEY_SIZE_MAX (16) #define CFG_ENCRYPTION_KEY_SIZE_MIN (8) /** * Define IO capabilities */ -#define CFG_IO_CAPABILITY_DISPLAY_ONLY (0x00) -#define CFG_IO_CAPABILITY_DISPLAY_YES_NO (0x01) -#define CFG_IO_CAPABILITY_KEYBOARD_ONLY (0x02) -#define CFG_IO_CAPABILITY_NO_INPUT_NO_OUTPUT (0x03) -#define CFG_IO_CAPABILITY_KEYBOARD_DISPLAY (0x04) - -#define CFG_IO_CAPABILITY CFG_IO_CAPABILITY_DISPLAY_YES_NO +#define CFG_IO_CAPABILITY IO_CAP_DISPLAY_YES_NO /** * Define MITM modes */ -#define CFG_MITM_PROTECTION_NOT_REQUIRED (0x00) -#define CFG_MITM_PROTECTION_REQUIRED (0x01) - -#define CFG_MITM_PROTECTION CFG_MITM_PROTECTION_REQUIRED +#define CFG_MITM_PROTECTION MITM_PROTECTION_REQUIRED /** * Define Secure Connections Support */ -#define CFG_SECURE_NOT_SUPPORTED (0x00) -#define CFG_SECURE_OPTIONAL (0x01) -#define CFG_SECURE_MANDATORY (0x02) - -#define CFG_SC_SUPPORT CFG_SECURE_OPTIONAL - -/** - * Define Keypress Notification Support - */ -#define CFG_KEYPRESS_NOT_SUPPORTED (0x00) -#define CFG_KEYPRESS_SUPPORTED (0x01) - -#define CFG_KEYPRESS_NOTIFICATION_SUPPORT CFG_KEYPRESS_NOT_SUPPORTED - -/** - * Numeric Comparison Answers - */ -#define YES (0x01) -#define NO (0x00) - -/** - * Device name configuration for Generic Access Service - */ -#define CFG_GAP_DEVICE_NAME "TEMPLATE" -#define CFG_GAP_DEVICE_NAME_LENGTH (8) +#define CFG_SC_SUPPORT SC_PAIRING_OPTIONAL /** * Define PHY @@ -87,42 +39,6 @@ #define RX_1M 0x01 #define RX_2M 0x02 -/** -* Identity root key used to derive LTK and CSRK -*/ -#define CFG_BLE_IRK \ - { \ - 0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0x12, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, \ - 0xf0 \ - } - -/** -* Encryption root key used to derive LTK and CSRK -*/ -#define CFG_BLE_ERK \ - { \ - 0xfe, 0xdc, 0xba, 0x09, 0x87, 0x65, 0x43, 0x21, 0xfe, 0xdc, 0xba, 0x09, 0x87, 0x65, 0x43, \ - 0x21 \ - } - -/* USER CODE BEGIN Generic_Parameters */ -/** - * SMPS supply - * SMPS not used when Set to 0 - * SMPS used when Set to 1 - */ -#define CFG_USE_SMPS 1 -/* USER CODE END Generic_Parameters */ - -/**< specific parameters */ -/*****************************************************/ - -/** -* AD Element - Group B Feature -*/ -/* LSB - Second Byte */ -#define CFG_FEATURE_OTA_REBOOT (0x20) - /****************************************************************************** * BLE Stack ******************************************************************************/ @@ -203,7 +119,9 @@ * 1 : external high speed crystal HSE/32/32 * 0 : external low speed crystal ( no calibration ) */ -#define CFG_BLE_LSE_SOURCE 0 +#define CFG_BLE_LSE_SOURCE \ + SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE | SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV | \ + SHCI_C2_BLE_INIT_CFG_BLE_LS_CALIB /** * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us) @@ -253,8 +171,8 @@ */ #define CFG_BLE_OPTIONS \ (SHCI_C2_BLE_INIT_OPTIONS_LL_HOST | SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC | \ - SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW | SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV | \ - SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2 | SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3) + SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RO | SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV | \ + SHCI_C2_BLE_INIT_OPTIONS_CS_ALGO2 | SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3) /** * Queue length of BLE Event @@ -282,187 +200,3 @@ 255 /**< Set to 255 with the memory manager and the mailbox */ #define TL_BLE_EVENT_FRAME_SIZE (TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE) -/****************************************************************************** - * UART interfaces - ******************************************************************************/ - -/** - * Select UART interfaces - */ -#define CFG_DEBUG_TRACE_UART hw_uart1 -#define CFG_CONSOLE_MENU 0 - -/****************************************************************************** - * Low Power - ******************************************************************************/ -/** - * When set to 1, the low power mode is enable - * When set to 0, the device stays in RUN mode - */ -#define CFG_LPM_SUPPORTED 1 - -/****************************************************************************** - * Timer Server - ******************************************************************************/ -/** - * CFG_RTC_WUCKSEL_DIVIDER: This sets the RTCCLK divider to the wakeup timer. - * The lower is the value, the better is the power consumption and the accuracy of the timerserver - * The higher is the value, the finest is the granularity - * - * CFG_RTC_ASYNCH_PRESCALER: This sets the asynchronous prescaler of the RTC. It should as high as possible ( to ouput - * clock as low as possible) but the output clock should be equal or higher frequency compare to the clock feeding - * the wakeup timer. A lower clock speed would impact the accuracy of the timer server. - * - * CFG_RTC_SYNCH_PRESCALER: This sets the synchronous prescaler of the RTC. - * When the 1Hz calendar clock is required, it shall be sets according to other settings - * When the 1Hz calendar clock is not needed, CFG_RTC_SYNCH_PRESCALER should be set to 0x7FFF (MAX VALUE) - * - * CFG_RTCCLK_DIVIDER_CONF: - * Shall be set to either 0,2,4,8,16 - * When set to either 2,4,8,16, the 1Hhz calendar is supported - * When set to 0, the user sets its own configuration - * - * The following settings are computed with LSI as input to the RTC - */ -#define CFG_RTCCLK_DIVIDER_CONF 0 - -#if(CFG_RTCCLK_DIVIDER_CONF == 0) -/** - * Custom configuration - * It does not support 1Hz calendar - * It divides the RTC CLK by 16 - */ -#define CFG_RTCCLK_DIV (16) -#define CFG_RTC_WUCKSEL_DIVIDER (0) -#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1) -#define CFG_RTC_SYNCH_PRESCALER (0x7FFF) - -#else - -#if(CFG_RTCCLK_DIVIDER_CONF == 2) -/** - * It divides the RTC CLK by 2 - */ -#define CFG_RTC_WUCKSEL_DIVIDER (3) -#endif - -#if(CFG_RTCCLK_DIVIDER_CONF == 4) -/** - * It divides the RTC CLK by 4 - */ -#define CFG_RTC_WUCKSEL_DIVIDER (2) -#endif - -#if(CFG_RTCCLK_DIVIDER_CONF == 8) -/** - * It divides the RTC CLK by 8 - */ -#define CFG_RTC_WUCKSEL_DIVIDER (1) -#endif - -#if(CFG_RTCCLK_DIVIDER_CONF == 16) -/** - * It divides the RTC CLK by 16 - */ -#define CFG_RTC_WUCKSEL_DIVIDER (0) -#endif - -#define CFG_RTCCLK_DIV CFG_RTCCLK_DIVIDER_CONF -#define CFG_RTC_ASYNCH_PRESCALER (CFG_RTCCLK_DIV - 1) -#define CFG_RTC_SYNCH_PRESCALER (DIVR(LSE_VALUE, (CFG_RTC_ASYNCH_PRESCALER + 1)) - 1) - -#endif - -/** tick timer value in us */ -#define CFG_TS_TICK_VAL DIVR((CFG_RTCCLK_DIV * 1000000), LSE_VALUE) - -typedef enum { - CFG_TIM_PROC_ID_ISR, - /* USER CODE BEGIN CFG_TimProcID_t */ - - /* USER CODE END CFG_TimProcID_t */ -} CFG_TimProcID_t; - -/****************************************************************************** - * Debug - ******************************************************************************/ -/** - * When set, this resets some hw resources to set the device in the same state than the power up - * The FW resets only register that may prevent the FW to run properly - * - * This shall be set to 0 in a final product - * - */ -#define CFG_HW_RESET_BY_FW 0 - -/** - * keep debugger enabled while in any low power mode when set to 1 - * should be set to 0 in production - */ -#define CFG_DEBUGGER_SUPPORTED 1 - -/** - * When set to 1, the traces are enabled in the BLE services - */ -#define CFG_DEBUG_BLE_TRACE 0 - -/** - * Enable or Disable traces in application - */ -#define CFG_DEBUG_APP_TRACE 0 - -#if(CFG_DEBUG_APP_TRACE != 0) -#define APP_DBG_MSG PRINT_MESG_DBG -#else -#define APP_DBG_MSG PRINT_NO_MESG -#endif - -#if((CFG_DEBUG_BLE_TRACE != 0) || (CFG_DEBUG_APP_TRACE != 0)) -#define CFG_DEBUG_TRACE 1 -#endif - -#if(CFG_DEBUG_TRACE != 0) -#undef CFG_LPM_SUPPORTED -#undef CFG_DEBUGGER_SUPPORTED -#define CFG_LPM_SUPPORTED 0 -#define CFG_DEBUGGER_SUPPORTED 1 -#endif - -/** - * When CFG_DEBUG_TRACE_FULL is set to 1, the trace are output with the API name, the file name and the line number - * When CFG_DEBUG_TRACE_LIGHT is set to 1, only the debug message is output - * - * When both are set to 0, no trace are output - * When both are set to 1, CFG_DEBUG_TRACE_FULL is selected - */ -#define CFG_DEBUG_TRACE_LIGHT 0 -#define CFG_DEBUG_TRACE_FULL 0 - -#if((CFG_DEBUG_TRACE != 0) && (CFG_DEBUG_TRACE_LIGHT == 0) && (CFG_DEBUG_TRACE_FULL == 0)) -#undef CFG_DEBUG_TRACE_FULL -#undef CFG_DEBUG_TRACE_LIGHT -#define CFG_DEBUG_TRACE_FULL 0 -#define CFG_DEBUG_TRACE_LIGHT 1 -#endif - -#if(CFG_DEBUG_TRACE == 0) -#undef CFG_DEBUG_TRACE_FULL -#undef CFG_DEBUG_TRACE_LIGHT -#define CFG_DEBUG_TRACE_FULL 0 -#define CFG_DEBUG_TRACE_LIGHT 0 -#endif - -/** - * When not set, the traces is looping on sending the trace over UART - */ -#define DBG_TRACE_USE_CIRCULAR_QUEUE 0 - -/** - * max buffer Size to queue data traces and max data trace allowed. - * Only Used if DBG_TRACE_USE_CIRCULAR_QUEUE is defined - */ -#define DBG_TRACE_MSG_QUEUE_SIZE 4096 -#define MAX_DBG_TRACE_MSG_SIZE 1024 - -#define CFG_OTP_BASE_ADDRESS OTP_AREA_BASE -#define CFG_OTP_END_ADRESS OTP_AREA_END_ADDR diff --git a/firmware/targets/f7/ble_glue/app_debug.c b/firmware/targets/f7/ble_glue/app_debug.c index d28852822..fe76687b9 100644 --- a/firmware/targets/f7/ble_glue/app_debug.c +++ b/firmware/targets/f7/ble_glue/app_debug.c @@ -6,6 +6,9 @@ #include #include +#include "stm32wbxx_ll_bus.h" +#include "stm32wbxx_ll_pwr.h" + #include typedef PACKED_STRUCT { @@ -108,10 +111,6 @@ static void APPD_SetCPU2GpioConfig(void); static void APPD_BleDtbCfg(void); void APPD_Init() { -#if(CFG_DEBUG_TRACE != 0) - DbgTraceInit(); -#endif - APPD_SetCPU2GpioConfig(); APPD_BleDtbCfg(); } @@ -252,13 +251,3 @@ static void APPD_BleDtbCfg(void) { } #endif } - -#if(CFG_DEBUG_TRACE != 0) -void DbgOutputInit(void) { -} - -void DbgOutputTraces(uint8_t* p_data, uint16_t size, void (*cb)(void)) { - furi_hal_console_tx(p_data, size); - cb(); -} -#endif diff --git a/firmware/targets/f7/ble_glue/app_debug.h b/firmware/targets/f7/ble_glue/app_debug.h index 92a54d75b..213470bed 100644 --- a/firmware/targets/f7/ble_glue/app_debug.h +++ b/firmware/targets/f7/ble_glue/app_debug.h @@ -1,26 +1,4 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : app_debug.h - * Description : Header for app_debug.c module - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __APP_DEBUG_H -#define __APP_DEBUG_H +#pragma once #ifdef __cplusplus extern "C" { @@ -32,7 +10,3 @@ void APPD_EnableCPU2(void); #ifdef __cplusplus } #endif - -#endif /*__APP_DEBUG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/targets/f7/ble_glue/ble_app.c b/firmware/targets/f7/ble_glue/ble_app.c index c0418d9fe..548a86e19 100644 --- a/firmware/targets/f7/ble_glue/ble_app.c +++ b/firmware/targets/f7/ble_glue/ble_app.c @@ -18,8 +18,8 @@ PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t ble_app_cmd_buffer; PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint32_t ble_app_nvm[BLE_NVM_SRAM_SIZE]; _Static_assert( - sizeof(SHCI_C2_Ble_Init_Cmd_Packet_t) == 57, - "Ble stack config structure size mismatch (check new config options - last updated for v.1.15.0)"); + sizeof(SHCI_C2_Ble_Init_Cmd_Packet_t) == 58, + "Ble stack config structure size mismatch (check new config options - last updated for v.1.17.2)"); typedef struct { FuriMutex* hci_mtx; @@ -72,10 +72,13 @@ static const SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet = { .rx_model_config = 1, /* New stack (13.3->15.0) */ .max_adv_set_nbr = 1, // Only used if SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV is set - .max_adv_data_len = 31, // Only used if SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV is set + .max_adv_data_len = 1650, // Only used if SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV is set .tx_path_compens = 0, // RF TX Path Compensation, * 0.1 dB .rx_path_compens = 0, // RF RX Path Compensation, * 0.1 dB - .ble_core_version = 11, // BLE Core Version: 11(5.2), 12(5.3) + .ble_core_version = SHCI_C2_BLE_INIT_BLE_CORE_5_4, + /*15.0->17.0*/ + .Options_extension = SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED | + SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY, }}; bool ble_app_init() { diff --git a/firmware/targets/f7/ble_glue/ble_app.h b/firmware/targets/f7/ble_glue/ble_app.h index 495005ec4..2e6babab7 100644 --- a/firmware/targets/f7/ble_glue/ble_app.h +++ b/firmware/targets/f7/ble_glue/ble_app.h @@ -1,12 +1,12 @@ #pragma once +#include +#include + #ifdef __cplusplus extern "C" { #endif -#include -#include - bool ble_app_init(); void ble_app_get_key_storage_buff(uint8_t** addr, uint16_t* size); void ble_app_thread_stop(); diff --git a/firmware/targets/f7/ble_glue/ble_conf.h b/firmware/targets/f7/ble_glue/ble_conf.h index a04d1def1..2b9c22dfe 100644 --- a/firmware/targets/f7/ble_glue/ble_conf.h +++ b/firmware/targets/f7/ble_glue/ble_conf.h @@ -1,51 +1,7 @@ -/** - ****************************************************************************** - * File Name : App/ble_conf.h - * Description : Configuration file for BLE Middleware. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef BLE_CONF_H -#define BLE_CONF_H +#pragma once #include "app_conf.h" -#ifndef __weak -#define __weak __attribute__((weak)) -#endif - -/****************************************************************************** - * - * BLE SERVICES CONFIGURATION - * blesvc - * - ******************************************************************************/ - -/** - * This setting shall be set to '1' if the device needs to support the Peripheral Role - * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1' - */ -#define BLE_CFG_PERIPHERAL 1 - -/** - * This setting shall be set to '1' if the device needs to support the Central Role - * In the MS configuration, both BLE_CFG_PERIPHERAL and BLE_CFG_CENTRAL shall be set to '1' - */ -#define BLE_CFG_CENTRAL 0 - /** * There is one handler per service enabled * Note: There is no handler for the Device Information Service @@ -56,18 +12,3 @@ #define BLE_CFG_SVC_MAX_NBR_CB 7 #define BLE_CFG_CLT_MAX_NBR_CB 0 - -/****************************************************************************** - * GAP Service - Apprearance - ******************************************************************************/ - -#define BLE_CFG_UNKNOWN_APPEARANCE (0) -#define BLE_CFG_GAP_APPEARANCE (0x0086) - -/****************************************************************************** - * Over The Air Feature (OTA) - STM Proprietary - ******************************************************************************/ -#define BLE_CFG_OTA_REBOOT_CHAR 0 /**< REBOOT OTA MODE CHARACTERISTIC */ - -#endif /*BLE_CONF_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/targets/f7/ble_glue/ble_const.h b/firmware/targets/f7/ble_glue/ble_const.h index 85f734b62..1e6647d90 100644 --- a/firmware/targets/f7/ble_glue/ble_const.h +++ b/firmware/targets/f7/ble_glue/ble_const.h @@ -1,22 +1,4 @@ -/***************************************************************************** - * @file ble_const.h - * @author MDG - * @brief This file contains the definitions which are compiler dependent. - ***************************************************************************** - * @attention - * - * Copyright (c) 2018-2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ***************************************************************************** - */ - -#ifndef BLE_CONST_H__ -#define BLE_CONST_H__ +#pragma once #include #include @@ -115,5 +97,3 @@ extern int hci_send_req(struct hci_request* req, uint8_t async); #ifndef MAX #define MAX(a, b) (((a) > (b)) ? (a) : (b)) #endif - -#endif /* BLE_CONST_H__ */ diff --git a/firmware/targets/f7/ble_glue/ble_dbg_conf.h b/firmware/targets/f7/ble_glue/ble_dbg_conf.h index 8305f8106..6f70f09be 100644 --- a/firmware/targets/f7/ble_glue/ble_dbg_conf.h +++ b/firmware/targets/f7/ble_glue/ble_dbg_conf.h @@ -1,199 +1 @@ -/** - ****************************************************************************** - * File Name : App/ble_dbg_conf.h - * Description : Debug configuration file for BLE Middleware. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __BLE_DBG_CONF_H -#define __BLE_DBG_CONF_H - -/** - * Enable or Disable traces from BLE - */ - -#define BLE_DBG_APP_EN 1 -#define BLE_DBG_DIS_EN 1 -#define BLE_DBG_HRS_EN 1 -#define BLE_DBG_SVCCTL_EN 1 -#define BLE_DBG_BLS_EN 1 -#define BLE_DBG_HTS_EN 1 -#define BLE_DBG_P2P_STM_EN 1 - -/** - * Macro definition - */ -#if(BLE_DBG_APP_EN != 0) -#define BLE_DBG_APP_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_APP_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_DIS_EN != 0) -#define BLE_DBG_DIS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_DIS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_HRS_EN != 0) -#define BLE_DBG_HRS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_HRS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_P2P_STM_EN != 0) -#define BLE_DBG_P2P_STM_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_P2P_STM_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_TEMPLATE_STM_EN != 0) -#define BLE_DBG_TEMPLATE_STM_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_TEMPLATE_STM_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_EDS_STM_EN != 0) -#define BLE_DBG_EDS_STM_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_EDS_STM_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_LBS_STM_EN != 0) -#define BLE_DBG_LBS_STM_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_LBS_STM_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_SVCCTL_EN != 0) -#define BLE_DBG_SVCCTL_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_SVCCTL_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_CTS_EN != 0) -#define BLE_DBG_CTS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_CTS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_HIDS_EN != 0) -#define BLE_DBG_HIDS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_HIDS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_PASS_EN != 0) -#define BLE_DBG_PASS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_PASS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_BLS_EN != 0) -#define BLE_DBG_BLS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_BLS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_HTS_EN != 0) -#define BLE_DBG_HTS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_HTS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_ANS_EN != 0) -#define BLE_DBG_ANS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_ANS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_ESS_EN != 0) -#define BLE_DBG_ESS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_ESS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_GLS_EN != 0) -#define BLE_DBG_GLS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_GLS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_BAS_EN != 0) -#define BLE_DBG_BAS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_BAS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_RTUS_EN != 0) -#define BLE_DBG_RTUS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_RTUS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_HPS_EN != 0) -#define BLE_DBG_HPS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_HPS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_TPS_EN != 0) -#define BLE_DBG_TPS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_TPS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_LLS_EN != 0) -#define BLE_DBG_LLS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_LLS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_IAS_EN != 0) -#define BLE_DBG_IAS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_IAS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_WSS_EN != 0) -#define BLE_DBG_WSS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_WSS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_LNS_EN != 0) -#define BLE_DBG_LNS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_LNS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_SCPS_EN != 0) -#define BLE_DBG_SCPS_MSG PRINT_MESG_DBG -#else -#define BLE_DBG_SCPS_MSG PRINT_NO_MESG -#endif - -#if(BLE_DBG_DTS_EN != 0) -#define BLE_DBG_DTS_MSG PRINT_MESG_DBG -#define BLE_DBG_DTS_BUF PRINT_LOG_BUFF_DBG -#else -#define BLE_DBG_DTS_MSG PRINT_NO_MESG -#define BLE_DBG_DTS_BUF PRINT_NO_MESG -#endif - -#endif /*__BLE_DBG_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#pragma once diff --git a/firmware/targets/f7/ble_glue/ble_glue.c b/firmware/targets/f7/ble_glue/ble_glue.c index 2c30612b5..5f129ba8c 100644 --- a/firmware/targets/f7/ble_glue/ble_glue.c +++ b/firmware/targets/f7/ble_glue/ble_glue.c @@ -32,7 +32,6 @@ static uint8_t ble_glue_ble_spare_event_buff[sizeof(TL_PacketHeader_t) + TL_EVT_ typedef struct { FuriMutex* shci_mtx; - FuriSemaphore* shci_sem; FuriThread* thread; BleGlueStatus status; BleGlueKeyStorageChangedCallback callback; @@ -104,7 +103,6 @@ void ble_glue_init() { TL_Init(); ble_glue->shci_mtx = furi_mutex_alloc(FuriMutexTypeNormal); - ble_glue->shci_sem = furi_semaphore_alloc(1, 0); // FreeRTOS system task creation ble_glue->thread = furi_thread_alloc_ex("BleShciDriver", 1024, ble_glue_shci_thread, ble_glue); @@ -393,7 +391,6 @@ void ble_glue_thread_stop() { furi_thread_free(ble_glue->thread); // Free resources furi_mutex_free(ble_glue->shci_mtx); - furi_semaphore_free(ble_glue->shci_sem); ble_glue_clear_shared_memory(); free(ble_glue); ble_glue = NULL; @@ -427,22 +424,6 @@ void shci_notify_asynch_evt(void* pdata) { } } -void shci_cmd_resp_release(uint32_t flag) { - UNUSED(flag); - if(ble_glue) { - furi_semaphore_release(ble_glue->shci_sem); - } -} - -void shci_cmd_resp_wait(uint32_t timeout) { - UNUSED(timeout); - if(ble_glue) { - furi_hal_power_insomnia_enter(); - furi_semaphore_acquire(ble_glue->shci_sem, FuriWaitForever); - furi_hal_power_insomnia_exit(); - } -} - bool ble_glue_reinit_c2() { return SHCI_C2_Reinit() == SHCI_Success; } diff --git a/firmware/targets/f7/ble_glue/compiler.h b/firmware/targets/f7/ble_glue/compiler.h index 98a93d712..1d32c2a2e 100644 --- a/firmware/targets/f7/ble_glue/compiler.h +++ b/firmware/targets/f7/ble_glue/compiler.h @@ -1,22 +1,4 @@ -/***************************************************************************** - * @file compiler.h - * @author MDG - * @brief This file contains the definitions which are compiler dependent. - ***************************************************************************** - * @attention - * - * Copyright (c) 2018-2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ***************************************************************************** - */ - -#ifndef COMPILER_H__ -#define COMPILER_H__ +#pragma once #ifndef __PACKED_STRUCT #define __PACKED_STRUCT PACKED(struct) @@ -154,5 +136,3 @@ #endif #endif #endif - -#endif /* COMPILER_H__ */ diff --git a/firmware/targets/f7/ble_glue/hsem_map.h b/firmware/targets/f7/ble_glue/hsem_map.h new file mode 100644 index 000000000..9a5f51d20 --- /dev/null +++ b/firmware/targets/f7/ble_glue/hsem_map.h @@ -0,0 +1,81 @@ +#pragma once + +/****************************************************************************** + * Semaphores + * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+ + *****************************************************************************/ +/** +* Index of the semaphore used the prevent conflicts after standby sleep. +* Each CPUs takes this semaphore at standby wakeup until conflicting elements are restored. +*/ +#define CFG_HW_PWR_STANDBY_SEMID 10 +/** +* The CPU2 may be configured to store the Thread persistent data either in internal NVM storage on CPU2 or in +* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config() +* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed. +* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be: +* + CPU1 takes CFG_HW_THREAD_NVM_SRAM_SEMID semaphore +* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1) +* + CPU1 releases CFG_HW_THREAD_NVM_SRAM_SEMID semaphore +* CFG_HW_THREAD_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them. +* There is no timing constraint on how long this semaphore can be kept. +*/ +#define CFG_HW_THREAD_NVM_SRAM_SEMID 9 + +/** +* The CPU2 may be configured to store the BLE persistent data either in internal NVM storage on CPU2 or in +* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config() +* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed. +* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be: +* + CPU1 takes CFG_HW_BLE_NVM_SRAM_SEMID semaphore +* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1) +* + CPU1 releases CFG_HW_BLE_NVM_SRAM_SEMID semaphore +* CFG_HW_BLE_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them. +* There is no timing constraint on how long this semaphore can be kept. +*/ +#define CFG_HW_BLE_NVM_SRAM_SEMID 8 + +/** +* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash +* The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2 +* When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just +* after writing a raw (64bits data) or erasing one sector. +* Once the Semaphore has been released, there shall be at least 1us before it can be taken again. This is required +* to give the opportunity to CPU2 to take it. +* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit. +* By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore +* instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl() +*/ +#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7 + +/** +* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash +* In order to protect its timing, the CPU1 may get this semaphore to prevent the CPU2 to either +* write or erase in flash (as this will stall both CPUs) +* The PES bit shall not be used as this may stall the CPU2 in some cases. +*/ +#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6 + +/** +* Index of the semaphore used to manage the CLK48 clock configuration +* When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB +* and should be released after the application switch OFF the clock when the USB is not used anymore +* When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48. +* More details in AN5289 +*/ +#define CFG_HW_CLK48_CONFIG_SEMID 5 + +/* Index of the semaphore used to manage the entry Stop Mode procedure */ +#define CFG_HW_ENTRY_STOP_MODE_SEMID 4 + +/* Index of the semaphore used to access the RCC */ +#define CFG_HW_RCC_SEMID 3 + +/* Index of the semaphore used to access the FLASH */ +#define CFG_HW_FLASH_SEMID 2 + +/* Index of the semaphore used to access the PKA */ +#define CFG_HW_PKA_SEMID 1 + +/* Index of the semaphore used to access the RNG */ +#define CFG_HW_RNG_SEMID 0 diff --git a/firmware/targets/f7/ble_glue/hw_conf.h b/firmware/targets/f7/ble_glue/hw_conf.h deleted file mode 100644 index bf18a7d0e..000000000 --- a/firmware/targets/f7/ble_glue/hw_conf.h +++ /dev/null @@ -1,231 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file hw_conf.h - * @author MCD Application Team - * @brief Configuration of hardware interface - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef HW_CONF_H -#define HW_CONF_H - -#include "FreeRTOSConfig.h" - -/****************************************************************************** - * Semaphores - * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+ - *****************************************************************************/ -/** -* Index of the semaphore used the prevent conflicts after standby sleep. -* Each CPUs takes this semaphore at standby wakeup until conclicting elements are restored. -*/ -#define CFG_HW_PWR_STANDBY_SEMID 10 -/** -* The CPU2 may be configured to store the Thread persistent data either in internal NVM storage on CPU2 or in -* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config() -* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed. -* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be: -* + CPU1 takes CFG_HW_THREAD_NVM_SRAM_SEMID semaphore -* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1) -* + CPU1 releases CFG_HW_THREAD_NVM_SRAM_SEMID semaphore -* CFG_HW_THREAD_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them. -* There is no timing constraint on how long this semaphore can be kept. -*/ -#define CFG_HW_THREAD_NVM_SRAM_SEMID 9 - -/** -* The CPU2 may be configured to store the BLE persistent data either in internal NVM storage on CPU2 or in -* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config() -* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed. -* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be: -* + CPU1 takes CFG_HW_BLE_NVM_SRAM_SEMID semaphore -* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1) -* + CPU1 releases CFG_HW_BLE_NVM_SRAM_SEMID semaphore -* CFG_HW_BLE_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them. -* There is no timing constraint on how long this semaphore can be kept. -*/ -#define CFG_HW_BLE_NVM_SRAM_SEMID 8 - -/** -* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash -* The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2 -* When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just -* after writing a raw (64bits data) or erasing one sector. -* Once the Semaphore has been released, there shall be at least 1us before it can be taken again. This is required -* to give the opportunity to CPU2 to take it. -* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit. -* By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore -* instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl() -*/ -#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7 - -/** -* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash -* In order to protect its timing, the CPU1 may get this semaphore to prevent the CPU2 to either -* write or erase in flash (as this will stall both CPUs) -* The PES bit shall not be used as this may stall the CPU2 in some cases. -*/ -#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6 - -/** -* Index of the semaphore used to manage the CLK48 clock configuration -* When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB -* and should be released after the application switch OFF the clock when the USB is not used anymore -* When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48. -* More details in AN5289 -*/ -#define CFG_HW_CLK48_CONFIG_SEMID 5 - -/* Index of the semaphore used to manage the entry Stop Mode procedure */ -#define CFG_HW_ENTRY_STOP_MODE_SEMID 4 - -/* Index of the semaphore used to access the RCC */ -#define CFG_HW_RCC_SEMID 3 - -/* Index of the semaphore used to access the FLASH */ -#define CFG_HW_FLASH_SEMID 2 - -/* Index of the semaphore used to access the PKA */ -#define CFG_HW_PKA_SEMID 1 - -/* Index of the semaphore used to access the RNG */ -#define CFG_HW_RNG_SEMID 0 - -/****************************************************************************** - * HW TIMER SERVER - *****************************************************************************/ -/** - * The user may define the maximum number of virtual timers supported. - * It shall not exceed 255 - */ -#define CFG_HW_TS_MAX_NBR_CONCURRENT_TIMER 6 - -/** - * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the - * wakeup timer. - * This setting is the preemptpriority part of the NVIC. - */ -#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_PREEMPTPRIO \ - (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) /* FreeRTOS requirement */ - -/** - * The user may define the priority in the NVIC of the RTC_WKUP interrupt handler that is used to manage the - * wakeup timer. - * This setting is the subpriority part of the NVIC. It does not exist on all processors. When it is not supported - * on the CPU, the setting is ignored - */ -#define CFG_HW_TS_NVIC_RTC_WAKEUP_IT_SUBPRIO 0 - -/** - * Define a critical section in the Timer server - * The Timer server does not support the API to be nested - * The Application shall either: - * a) Ensure this will never happen - * b) Define the critical section - * The default implementations is masking all interrupts using the PRIMASK bit - * The TimerServer driver uses critical sections to avoid context corruption. This is achieved with the macro - * TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION. When CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION is set - * to 1, all STM32 interrupts are masked with the PRIMASK bit of the CortexM CPU. It is possible to use the BASEPRI - * register of the CortexM CPU to keep allowed some interrupts with high priority. In that case, the user shall - * re-implement TIMER_ENTER_CRITICAL_SECTION and TIMER_EXIT_CRITICAL_SECTION and shall make sure that no TimerServer - * API are called when the TIMER critical section is entered - */ -#define CFG_HW_TS_USE_PRIMASK_AS_CRITICAL_SECTION 1 - -/** - * This value shall reflect the maximum delay there could be in the application between the time the RTC interrupt - * is generated by the Hardware and the time when the RTC interrupt handler is called. This time is measured in - * number of RTCCLK ticks. - * A relaxed timing would be 10ms - * When the value is too short, the timerserver will not be able to count properly and all timeout may be random. - * When the value is too long, the device may wake up more often than the most optimal configuration. However, the - * impact on power consumption would be marginal (unless the value selected is extremely too long). It is strongly - * recommended to select a value large enough to make sure it is not too short to ensure reliability of the system - * as this will have marginal impact on low power mode - */ -#define CFG_HW_TS_RTC_HANDLER_MAX_DELAY (10 * (LSI_VALUE / 1000)) - -/** - * Interrupt ID in the NVIC of the RTC Wakeup interrupt handler - * It shall be type of IRQn_Type - */ -#define CFG_HW_TS_RTC_WAKEUP_HANDLER_ID RTC_WKUP_IRQn - -/****************************************************************************** - * HW UART - *****************************************************************************/ -#define CFG_HW_LPUART1_ENABLED 0 -#define CFG_HW_LPUART1_DMA_TX_SUPPORTED 0 - -#define CFG_HW_USART1_ENABLED 1 -#define CFG_HW_USART1_DMA_TX_SUPPORTED 1 - -/** - * UART1 - */ -#define CFG_HW_USART1_PREEMPTPRIORITY 0x0F -#define CFG_HW_USART1_SUBPRIORITY 0 - -/** < The application shall check the selected source clock is enable */ -#define CFG_HW_USART1_SOURCE_CLOCK RCC_USART1CLKSOURCE_SYSCLK - -#define CFG_HW_USART1_BAUDRATE 115200 -#define CFG_HW_USART1_WORDLENGTH UART_WORDLENGTH_8B -#define CFG_HW_USART1_STOPBITS UART_STOPBITS_1 -#define CFG_HW_USART1_PARITY UART_PARITY_NONE -#define CFG_HW_USART1_HWFLOWCTL UART_HWCONTROL_NONE -#define CFG_HW_USART1_MODE UART_MODE_TX_RX -#define CFG_HW_USART1_ADVFEATUREINIT UART_ADVFEATURE_NO_INIT -#define CFG_HW_USART1_OVERSAMPLING UART_OVERSAMPLING_8 - -#define CFG_HW_USART1_TX_PORT_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define CFG_HW_USART1_TX_PORT GPIOB -#define CFG_HW_USART1_TX_PIN GPIO_PIN_6 -#define CFG_HW_USART1_TX_MODE GPIO_MODE_AF_PP -#define CFG_HW_USART1_TX_PULL GPIO_NOPULL -#define CFG_HW_USART1_TX_SPEED GPIO_SPEED_FREQ_VERY_HIGH -#define CFG_HW_USART1_TX_ALTERNATE GPIO_AF7_USART1 - -#define CFG_HW_USART1_RX_PORT_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define CFG_HW_USART1_RX_PORT GPIOB -#define CFG_HW_USART1_RX_PIN GPIO_PIN_7 -#define CFG_HW_USART1_RX_MODE GPIO_MODE_AF_PP -#define CFG_HW_USART1_RX_PULL GPIO_NOPULL -#define CFG_HW_USART1_RX_SPEED GPIO_SPEED_FREQ_VERY_HIGH -#define CFG_HW_USART1_RX_ALTERNATE GPIO_AF7_USART1 - -#define CFG_HW_USART1_CTS_PORT_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define CFG_HW_USART1_CTS_PORT GPIOA -#define CFG_HW_USART1_CTS_PIN GPIO_PIN_11 -#define CFG_HW_USART1_CTS_MODE GPIO_MODE_AF_PP -#define CFG_HW_USART1_CTS_PULL GPIO_PULLDOWN -#define CFG_HW_USART1_CTS_SPEED GPIO_SPEED_FREQ_VERY_HIGH -#define CFG_HW_USART1_CTS_ALTERNATE GPIO_AF7_USART1 - -#define CFG_HW_USART1_DMA_TX_PREEMPTPRIORITY 0x0F -#define CFG_HW_USART1_DMA_TX_SUBPRIORITY 0 - -#define CFG_HW_USART1_DMAMUX_CLK_ENABLE __HAL_RCC_DMAMUX1_CLK_ENABLE -#define CFG_HW_USART1_DMA_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define CFG_HW_USART1_TX_DMA_REQ DMA_REQUEST_USART1_TX -#define CFG_HW_USART1_TX_DMA_CHANNEL DMA2_Channel4 -#define CFG_HW_USART1_TX_DMA_IRQn DMA2_Channel4_IRQn -#define CFG_HW_USART1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler - -#endif /*HW_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/targets/f7/ble_glue/hw_if.h b/firmware/targets/f7/ble_glue/hw_if.h deleted file mode 100644 index a0ac23df3..000000000 --- a/firmware/targets/f7/ble_glue/hw_if.h +++ /dev/null @@ -1,102 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file hw_if.h - * @author MCD Application Team - * @brief Hardware Interface - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef HW_IF_H -#define HW_IF_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32wbxx.h" -#include "stm32wbxx_ll_exti.h" -#include "stm32wbxx_ll_system.h" -#include "stm32wbxx_ll_rcc.h" -#include "stm32wbxx_ll_ipcc.h" -#include "stm32wbxx_ll_bus.h" -#include "stm32wbxx_ll_pwr.h" -#include "stm32wbxx_ll_cortex.h" -#include "stm32wbxx_ll_utils.h" -#include "stm32wbxx_ll_hsem.h" -#include "stm32wbxx_ll_gpio.h" -#include "stm32wbxx_ll_rtc.h" - -#ifdef USE_STM32WBXX_USB_DONGLE -#include "stm32wbxx_usb_dongle.h" -#endif -#ifdef USE_STM32WBXX_NUCLEO -#include "stm32wbxx_nucleo.h" -#endif -#ifdef USE_X_NUCLEO_EPD -#include "x_nucleo_epd.h" -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/****************************************************************************** - * HW UART - ******************************************************************************/ -typedef enum { - hw_uart1, - hw_uart2, - hw_lpuart1, -} hw_uart_id_t; - -typedef enum { - hw_uart_ok, - hw_uart_error, - hw_uart_busy, - hw_uart_to, -} hw_status_t; - -void HW_UART_Init(hw_uart_id_t hw_uart_id); -void HW_UART_Receive_IT( - hw_uart_id_t hw_uart_id, - uint8_t* pData, - uint16_t Size, - void (*Callback)(void)); -void HW_UART_Transmit_IT( - hw_uart_id_t hw_uart_id, - uint8_t* pData, - uint16_t Size, - void (*Callback)(void)); -hw_status_t - HW_UART_Transmit(hw_uart_id_t hw_uart_id, uint8_t* p_data, uint16_t size, uint32_t timeout); -hw_status_t HW_UART_Transmit_DMA( - hw_uart_id_t hw_uart_id, - uint8_t* p_data, - uint16_t size, - void (*Callback)(void)); -void HW_UART_Interrupt_Handler(hw_uart_id_t hw_uart_id); -void HW_UART_DMA_Interrupt_Handler(hw_uart_id_t hw_uart_id); - -#ifdef __cplusplus -} -#endif - -#endif /*HW_IF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/targets/f7/ble_glue/hw_ipcc.c b/firmware/targets/f7/ble_glue/hw_ipcc.c index 7c84df09f..c2397f351 100644 --- a/firmware/targets/f7/ble_glue/hw_ipcc.c +++ b/firmware/targets/f7/ble_glue/hw_ipcc.c @@ -1,160 +1,52 @@ -/** - ****************************************************************************** - * File Name : Target/hw_ipcc.c - * Description : Hardware IPCC source file for STM32WPAN Middleware. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ #include "app_common.h" #include +#include +#include -/* Global variables ---------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -#define HW_IPCC_TX_PENDING(channel) \ - (!(LL_C1_IPCC_IsActiveFlag_CHx(IPCC, channel))) && (((~(IPCC->C1MR)) & ((channel) << 16U))) -#define HW_IPCC_RX_PENDING(channel) \ - (LL_C2_IPCC_IsActiveFlag_CHx(IPCC, channel)) && (((~(IPCC->C1MR)) & ((channel) << 0U))) +#include +#include -/* Private macros ------------------------------------------------------------*/ -/* Private typedef -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static void (*FreeBufCb)(void); +#include -/* Private function prototypes -----------------------------------------------*/ -static void HW_IPCC_BLE_EvtHandler(void); -static void HW_IPCC_BLE_AclDataEvtHandler(void); -static void HW_IPCC_MM_FreeBufHandler(void); -static void HW_IPCC_SYS_CmdEvtHandler(void); -static void HW_IPCC_SYS_EvtHandler(void); -static void HW_IPCC_TRACES_EvtHandler(void); +#define HW_IPCC_TX_PENDING(channel) \ + ((!(LL_C1_IPCC_IsActiveFlag_CHx(IPCC, channel))) && \ + LL_C1_IPCC_IsEnabledTransmitChannel(IPCC, channel)) +#define HW_IPCC_RX_PENDING(channel) \ + (LL_C2_IPCC_IsActiveFlag_CHx(IPCC, channel) && \ + LL_C1_IPCC_IsEnabledReceiveChannel(IPCC, channel)) -#ifdef THREAD_WB -static void HW_IPCC_OT_CmdEvtHandler(void); -static void HW_IPCC_THREAD_NotEvtHandler(void); -static void HW_IPCC_THREAD_CliNotEvtHandler(void); -#endif +static void (*FreeBufCb)(); -#ifdef LLD_TESTS_WB -static void HW_IPCC_LLDTESTS_ReceiveCliRspHandler(void); -static void HW_IPCC_LLDTESTS_ReceiveM0CmdHandler(void); -#endif -#ifdef LLD_BLE_WB -/*static void HW_IPCC_LLD_BLE_ReceiveCliRspHandler( void );*/ -static void HW_IPCC_LLD_BLE_ReceiveRspHandler(void); -static void HW_IPCC_LLD_BLE_ReceiveM0CmdHandler(void); -#endif +static void HW_IPCC_BLE_EvtHandler(); +static void HW_IPCC_BLE_AclDataEvtHandler(); +static void HW_IPCC_MM_FreeBufHandler(); +static void HW_IPCC_SYS_CmdEvtHandler(); +static void HW_IPCC_SYS_EvtHandler(); +static void HW_IPCC_TRACES_EvtHandler(); -#ifdef MAC_802_15_4_WB -static void HW_IPCC_MAC_802_15_4_CmdEvtHandler(void); -static void HW_IPCC_MAC_802_15_4_NotEvtHandler(void); -#endif - -#ifdef ZIGBEE_WB -static void HW_IPCC_ZIGBEE_CmdEvtHandler(void); -static void HW_IPCC_ZIGBEE_StackNotifEvtHandler(void); -static void HW_IPCC_ZIGBEE_StackM0RequestHandler(void); -#endif - -/* Public function definition -----------------------------------------------*/ - -/****************************************************************************** - * INTERRUPT HANDLER - ******************************************************************************/ -void HW_IPCC_Rx_Handler(void) { +void HW_IPCC_Rx_Handler() { if(HW_IPCC_RX_PENDING(HW_IPCC_SYSTEM_EVENT_CHANNEL)) { HW_IPCC_SYS_EvtHandler(); - } -#ifdef MAC_802_15_4_WB - else if(HW_IPCC_RX_PENDING(HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL)) { - HW_IPCC_MAC_802_15_4_NotEvtHandler(); - } -#endif /* MAC_802_15_4_WB */ -#ifdef THREAD_WB - else if(HW_IPCC_RX_PENDING(HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL)) { - HW_IPCC_THREAD_NotEvtHandler(); - } else if(HW_IPCC_RX_PENDING(HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL)) { - HW_IPCC_THREAD_CliNotEvtHandler(); - } -#endif /* THREAD_WB */ -#ifdef LLD_TESTS_WB - else if(HW_IPCC_RX_PENDING(HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL)) { - HW_IPCC_LLDTESTS_ReceiveCliRspHandler(); - } else if(HW_IPCC_RX_PENDING(HW_IPCC_LLDTESTS_M0_CMD_CHANNEL)) { - HW_IPCC_LLDTESTS_ReceiveM0CmdHandler(); - } -#endif /* LLD_TESTS_WB */ -#ifdef LLD_BLE_WB - else if(HW_IPCC_RX_PENDING(HW_IPCC_LLD_BLE_RSP_CHANNEL)) { - HW_IPCC_LLD_BLE_ReceiveRspHandler(); - } else if(HW_IPCC_RX_PENDING(HW_IPCC_LLD_BLE_M0_CMD_CHANNEL)) { - HW_IPCC_LLD_BLE_ReceiveM0CmdHandler(); - } -#endif /* LLD_TESTS_WB */ -#ifdef ZIGBEE_WB - else if(HW_IPCC_RX_PENDING(HW_IPCC_ZIGBEE_APPLI_NOTIF_ACK_CHANNEL)) { - HW_IPCC_ZIGBEE_StackNotifEvtHandler(); - } else if(HW_IPCC_RX_PENDING(HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL)) { - HW_IPCC_ZIGBEE_StackM0RequestHandler(); - } -#endif /* ZIGBEE_WB */ - else if(HW_IPCC_RX_PENDING(HW_IPCC_BLE_EVENT_CHANNEL)) { + } else if(HW_IPCC_RX_PENDING(HW_IPCC_BLE_EVENT_CHANNEL)) { HW_IPCC_BLE_EvtHandler(); } else if(HW_IPCC_RX_PENDING(HW_IPCC_TRACES_CHANNEL)) { HW_IPCC_TRACES_EvtHandler(); } - - return; } -void HW_IPCC_Tx_Handler(void) { +void HW_IPCC_Tx_Handler() { if(HW_IPCC_TX_PENDING(HW_IPCC_SYSTEM_CMD_RSP_CHANNEL)) { HW_IPCC_SYS_CmdEvtHandler(); - } -#ifdef MAC_802_15_4_WB - else if(HW_IPCC_TX_PENDING(HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL)) { - HW_IPCC_MAC_802_15_4_CmdEvtHandler(); - } -#endif /* MAC_802_15_4_WB */ -#ifdef THREAD_WB - else if(HW_IPCC_TX_PENDING(HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL)) { - HW_IPCC_OT_CmdEvtHandler(); - } -#endif /* THREAD_WB */ -#ifdef LLD_TESTS_WB -// No TX handler for LLD tests -#endif /* LLD_TESTS_WB */ -#ifdef ZIGBEE_WB - if(HW_IPCC_TX_PENDING(HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL)) { - HW_IPCC_ZIGBEE_CmdEvtHandler(); - } -#endif /* ZIGBEE_WB */ - else if(HW_IPCC_TX_PENDING(HW_IPCC_SYSTEM_CMD_RSP_CHANNEL)) { + } else if(HW_IPCC_TX_PENDING(HW_IPCC_SYSTEM_CMD_RSP_CHANNEL)) { HW_IPCC_SYS_CmdEvtHandler(); } else if(HW_IPCC_TX_PENDING(HW_IPCC_MM_RELEASE_BUFFER_CHANNEL)) { HW_IPCC_MM_FreeBufHandler(); } else if(HW_IPCC_TX_PENDING(HW_IPCC_HCI_ACL_DATA_CHANNEL)) { HW_IPCC_BLE_AclDataEvtHandler(); } - - return; } -/****************************************************************************** - * GENERAL - ******************************************************************************/ -void HW_IPCC_Enable(void) { + +void HW_IPCC_Enable() { /** * Such as IPCC IP available to the CPU2, it is required to keep the IPCC clock running when FUS is running on CPU2 and CPU1 enters deep sleep mode @@ -177,11 +69,9 @@ void HW_IPCC_Enable(void) { __SEV(); /* Set the internal event flag and send an event to the CPU2 */ __WFE(); /* Clear the internal event flag */ LL_PWR_EnableBootC2(); - - return; } -void HW_IPCC_Init(void) { +void HW_IPCC_Init() { LL_C1_IPCC_EnableIT_RXO(IPCC); LL_C1_IPCC_EnableIT_TXF(IPCC); @@ -189,366 +79,62 @@ void HW_IPCC_Init(void) { NVIC_EnableIRQ(IPCC_C1_RX_IRQn); NVIC_SetPriority(IPCC_C1_TX_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 6, 0)); NVIC_EnableIRQ(IPCC_C1_TX_IRQn); - - return; } -/****************************************************************************** - * BLE - ******************************************************************************/ -void HW_IPCC_BLE_Init(void) { +void HW_IPCC_BLE_Init() { LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_BLE_EVENT_CHANNEL); - - return; } -void HW_IPCC_BLE_SendCmd(void) { +void HW_IPCC_BLE_SendCmd() { LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_BLE_CMD_CHANNEL); - - return; } -static void HW_IPCC_BLE_EvtHandler(void) { +static void HW_IPCC_BLE_EvtHandler() { HW_IPCC_BLE_RxEvtNot(); LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_BLE_EVENT_CHANNEL); - - return; } -void HW_IPCC_BLE_SendAclData(void) { +void HW_IPCC_BLE_SendAclData() { LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL); LL_C1_IPCC_EnableTransmitChannel(IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL); - - return; } -static void HW_IPCC_BLE_AclDataEvtHandler(void) { +static void HW_IPCC_BLE_AclDataEvtHandler() { LL_C1_IPCC_DisableTransmitChannel(IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL); HW_IPCC_BLE_AclDataAckNot(); - - return; } -__weak void HW_IPCC_BLE_AclDataAckNot(void){}; -__weak void HW_IPCC_BLE_RxEvtNot(void){}; - -/****************************************************************************** - * SYSTEM - ******************************************************************************/ -void HW_IPCC_SYS_Init(void) { +void HW_IPCC_SYS_Init() { LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL); - - return; } -void HW_IPCC_SYS_SendCmd(void) { +void HW_IPCC_SYS_SendCmd() { LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL); - LL_C1_IPCC_EnableTransmitChannel(IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL); - return; + FuriHalCortexTimer timer = furi_hal_cortex_timer_get(33000000); + + while(LL_C1_IPCC_IsActiveFlag_CHx(IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL)) { + furi_check(!furi_hal_cortex_timer_is_expired(timer), "HW_IPCC_SYS_SendCmd timeout"); + } + + HW_IPCC_SYS_CmdEvtHandler(); } -static void HW_IPCC_SYS_CmdEvtHandler(void) { +static void HW_IPCC_SYS_CmdEvtHandler() { LL_C1_IPCC_DisableTransmitChannel(IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL); HW_IPCC_SYS_CmdEvtNot(); - - return; } -static void HW_IPCC_SYS_EvtHandler(void) { +static void HW_IPCC_SYS_EvtHandler() { HW_IPCC_SYS_EvtNot(); LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL); - - return; } -__weak void HW_IPCC_SYS_CmdEvtNot(void){}; -__weak void HW_IPCC_SYS_EvtNot(void){}; - -/****************************************************************************** - * MAC 802.15.4 - ******************************************************************************/ -#ifdef MAC_802_15_4_WB -void HW_IPCC_MAC_802_15_4_Init(void) { - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL); - - return; -} - -void HW_IPCC_MAC_802_15_4_SendCmd(void) { - LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL); - LL_C1_IPCC_EnableTransmitChannel(IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL); - - return; -} - -void HW_IPCC_MAC_802_15_4_SendAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL); - - return; -} - -static void HW_IPCC_MAC_802_15_4_CmdEvtHandler(void) { - LL_C1_IPCC_DisableTransmitChannel(IPCC, HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL); - - HW_IPCC_MAC_802_15_4_CmdEvtNot(); - - return; -} - -static void HW_IPCC_MAC_802_15_4_NotEvtHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL); - - HW_IPCC_MAC_802_15_4_EvtNot(); - - return; -} -__weak void HW_IPCC_MAC_802_15_4_CmdEvtNot(void){}; -__weak void HW_IPCC_MAC_802_15_4_EvtNot(void){}; -#endif - -/****************************************************************************** - * THREAD - ******************************************************************************/ -#ifdef THREAD_WB -void HW_IPCC_THREAD_Init(void) { - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL); - - return; -} - -void HW_IPCC_OT_SendCmd(void) { - LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL); - LL_C1_IPCC_EnableTransmitChannel(IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL); - - return; -} - -void HW_IPCC_CLI_SendCmd(void) { - LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL); - - return; -} - -void HW_IPCC_THREAD_SendAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL); - - return; -} - -void HW_IPCC_THREAD_CliSendAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL); - - return; -} - -static void HW_IPCC_OT_CmdEvtHandler(void) { - LL_C1_IPCC_DisableTransmitChannel(IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL); - - HW_IPCC_OT_CmdEvtNot(); - - return; -} - -static void HW_IPCC_THREAD_NotEvtHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL); - - HW_IPCC_THREAD_EvtNot(); - - return; -} - -static void HW_IPCC_THREAD_CliNotEvtHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL); - - HW_IPCC_THREAD_CliEvtNot(); - - return; -} - -__weak void HW_IPCC_OT_CmdEvtNot(void){}; -__weak void HW_IPCC_CLI_CmdEvtNot(void){}; -__weak void HW_IPCC_THREAD_EvtNot(void){}; - -#endif /* THREAD_WB */ - -/****************************************************************************** - * LLD TESTS - ******************************************************************************/ -#ifdef LLD_TESTS_WB -void HW_IPCC_LLDTESTS_Init(void) { - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLDTESTS_M0_CMD_CHANNEL); - return; -} - -void HW_IPCC_LLDTESTS_SendCliCmd(void) { - LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_LLDTESTS_CLI_CMD_CHANNEL); - return; -} - -static void HW_IPCC_LLDTESTS_ReceiveCliRspHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL); - HW_IPCC_LLDTESTS_ReceiveCliRsp(); - return; -} - -void HW_IPCC_LLDTESTS_SendCliRspAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL); - return; -} - -static void HW_IPCC_LLDTESTS_ReceiveM0CmdHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_LLDTESTS_M0_CMD_CHANNEL); - HW_IPCC_LLDTESTS_ReceiveM0Cmd(); - return; -} - -void HW_IPCC_LLDTESTS_SendM0CmdAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_LLDTESTS_M0_CMD_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLDTESTS_M0_CMD_CHANNEL); - return; -} -__weak void HW_IPCC_LLDTESTS_ReceiveCliRsp(void){}; -__weak void HW_IPCC_LLDTESTS_ReceiveM0Cmd(void){}; -#endif /* LLD_TESTS_WB */ - -/****************************************************************************** - * LLD BLE - ******************************************************************************/ -#ifdef LLD_BLE_WB -void HW_IPCC_LLD_BLE_Init(void) { - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLD_BLE_RSP_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLD_BLE_M0_CMD_CHANNEL); - return; -} - -void HW_IPCC_LLD_BLE_SendCliCmd(void) { - LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_LLD_BLE_CLI_CMD_CHANNEL); - return; -} - -/*static void HW_IPCC_LLD_BLE_ReceiveCliRspHandler( void ) -{ - LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_LLD_BLE_CLI_RSP_CHANNEL ); - HW_IPCC_LLD_BLE_ReceiveCliRsp(); - return; -}*/ - -void HW_IPCC_LLD_BLE_SendCliRspAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_LLD_BLE_CLI_RSP_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLD_BLE_CLI_RSP_CHANNEL); - return; -} - -static void HW_IPCC_LLD_BLE_ReceiveM0CmdHandler(void) { - //LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_LLD_BLE_M0_CMD_CHANNEL ); - HW_IPCC_LLD_BLE_ReceiveM0Cmd(); - return; -} - -void HW_IPCC_LLD_BLE_SendM0CmdAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_LLD_BLE_M0_CMD_CHANNEL); - //LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_LLD_BLE_M0_CMD_CHANNEL ); - return; -} -__weak void HW_IPCC_LLD_BLE_ReceiveCliRsp(void){}; -__weak void HW_IPCC_LLD_BLE_ReceiveM0Cmd(void){}; - -/* Transparent Mode */ -void HW_IPCC_LLD_BLE_SendCmd(void) { - LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_LLD_BLE_CMD_CHANNEL); - return; -} - -static void HW_IPCC_LLD_BLE_ReceiveRspHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_LLD_BLE_RSP_CHANNEL); - HW_IPCC_LLD_BLE_ReceiveRsp(); - return; -} - -void HW_IPCC_LLD_BLE_SendRspAck(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_LLD_BLE_RSP_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_LLD_BLE_RSP_CHANNEL); - return; -} - -#endif /* LLD_BLE_WB */ - -/****************************************************************************** - * ZIGBEE - ******************************************************************************/ -#ifdef ZIGBEE_WB -void HW_IPCC_ZIGBEE_Init(void) { - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_ZIGBEE_APPLI_NOTIF_ACK_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL); - - return; -} - -void HW_IPCC_ZIGBEE_SendM4RequestToM0(void) { - LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL); - LL_C1_IPCC_EnableTransmitChannel(IPCC, HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL); - - return; -} - -void HW_IPCC_ZIGBEE_SendM4AckToM0Notify(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_ZIGBEE_APPLI_NOTIF_ACK_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_ZIGBEE_APPLI_NOTIF_ACK_CHANNEL); - - return; -} - -static void HW_IPCC_ZIGBEE_CmdEvtHandler(void) { - LL_C1_IPCC_DisableTransmitChannel(IPCC, HW_IPCC_ZIGBEE_CMD_APPLI_CHANNEL); - - HW_IPCC_ZIGBEE_RecvAppliAckFromM0(); - - return; -} - -static void HW_IPCC_ZIGBEE_StackNotifEvtHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_ZIGBEE_APPLI_NOTIF_ACK_CHANNEL); - - HW_IPCC_ZIGBEE_RecvM0NotifyToM4(); - - return; -} - -static void HW_IPCC_ZIGBEE_StackM0RequestHandler(void) { - LL_C1_IPCC_DisableReceiveChannel(IPCC, HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL); - - HW_IPCC_ZIGBEE_RecvM0RequestToM4(); - - return; -} - -void HW_IPCC_ZIGBEE_SendM4AckToM0Request(void) { - LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL); - LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL); - - return; -} - -__weak void HW_IPCC_ZIGBEE_RecvAppliAckFromM0(void){}; -__weak void HW_IPCC_ZIGBEE_RecvM0NotifyToM4(void){}; -__weak void HW_IPCC_ZIGBEE_RecvM0RequestToM4(void){}; -#endif /* ZIGBEE_WB */ - -/****************************************************************************** - * MEMORY MANAGER - ******************************************************************************/ -void HW_IPCC_MM_SendFreeBuf(void (*cb)(void)) { +void HW_IPCC_MM_SendFreeBuf(void (*cb)()) { if(LL_C1_IPCC_IsActiveFlag_CHx(IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL)) { FreeBufCb = cb; LL_C1_IPCC_EnableTransmitChannel(IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL); @@ -557,37 +143,22 @@ void HW_IPCC_MM_SendFreeBuf(void (*cb)(void)) { LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL); } - - return; } -static void HW_IPCC_MM_FreeBufHandler(void) { +static void HW_IPCC_MM_FreeBufHandler() { LL_C1_IPCC_DisableTransmitChannel(IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL); FreeBufCb(); LL_C1_IPCC_SetFlag_CHx(IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL); - - return; } -/****************************************************************************** - * TRACES - ******************************************************************************/ -void HW_IPCC_TRACES_Init(void) { +void HW_IPCC_TRACES_Init() { LL_C1_IPCC_EnableReceiveChannel(IPCC, HW_IPCC_TRACES_CHANNEL); - - return; } -static void HW_IPCC_TRACES_EvtHandler(void) { +static void HW_IPCC_TRACES_EvtHandler() { HW_IPCC_TRACES_EvtNot(); LL_C1_IPCC_ClearFlag_CHx(IPCC, HW_IPCC_TRACES_CHANNEL); - - return; } - -__weak void HW_IPCC_TRACES_EvtNot(void){}; - -/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/ diff --git a/firmware/targets/f7/ble_glue/osal.h b/firmware/targets/f7/ble_glue/osal.h index e5e0c4f68..0cde06179 100644 --- a/firmware/targets/f7/ble_glue/osal.h +++ b/firmware/targets/f7/ble_glue/osal.h @@ -1,25 +1,4 @@ -/***************************************************************************** - * @file osal.h - * @author MDG - * @brief This header file defines the OS abstraction layer used by - * the BLE stack. OSAL defines the set of functions which needs to be - * ported to target operating system and target platform. - * Actually, only memset, memcpy and memcmp wrappers are defined. - ***************************************************************************** - * @attention - * - * Copyright (c) 2018-2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ***************************************************************************** - */ - -#ifndef OSAL_H__ -#define OSAL_H__ +#pragma once /** * This function copies size number of bytes from a @@ -59,5 +38,3 @@ extern void* Osal_MemSet(void* ptr, int value, unsigned int size); * @return 0 if the two buffers are equal, 1 otherwise */ extern int Osal_MemCmp(const void* s1, const void* s2, unsigned int size); - -#endif /* OSAL_H__ */ diff --git a/firmware/targets/f7/ble_glue/tl_dbg_conf.h b/firmware/targets/f7/ble_glue/tl_dbg_conf.h index ce58af32b..daaa9d82b 100644 --- a/firmware/targets/f7/ble_glue/tl_dbg_conf.h +++ b/firmware/targets/f7/ble_glue/tl_dbg_conf.h @@ -1,39 +1,12 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : App/tl_dbg_conf.h - * Description : Debug configuration file for stm32wpan transport layer interface. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Ultimate Liberty license - * SLA0044, the "License"; You may not use this file except in compliance with - * the License. You may obtain a copy of the License at: - * www.st.com/SLA0044 - * - ****************************************************************************** - */ -/* USER CODE END Header */ +#pragma once -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __TL_DBG_CONF_H -#define __TL_DBG_CONF_H +#include "app_conf.h" /* required as some configuration used in dbg_trace.h are set there */ +#include "dbg_trace.h" #ifdef __cplusplus extern "C" { #endif -/* USER CODE BEGIN Tl_Conf */ - -/* Includes ------------------------------------------------------------------*/ -#include "app_conf.h" /* required as some configuration used in dbg_trace.h are set there */ -#include "dbg_trace.h" -#include "hw_if.h" - /** * Enable or Disable traces * The raw data output is the hci binary packet format as specified by the BT specification * @@ -124,12 +97,6 @@ extern "C" { #define TL_MM_DBG_MSG(...) #endif -/* USER CODE END Tl_Conf */ - #ifdef __cplusplus } #endif - -#endif /*__TL_DBG_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/targets/f7/ble_glue/utilities_conf.h b/firmware/targets/f7/ble_glue/utilities_conf.h deleted file mode 100644 index 9c15f2263..000000000 --- a/firmware/targets/f7/ble_glue/utilities_conf.h +++ /dev/null @@ -1,68 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : utilities_conf.h - * Description : Configuration file for STM32 Utilities. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef UTILITIES_CONF_H -#define UTILITIES_CONF_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include "cmsis_compiler.h" -#include "string.h" -#include - -/****************************************************************************** - * common - ******************************************************************************/ -#define UTILS_ENTER_CRITICAL_SECTION() FURI_CRITICAL_ENTER() - -#define UTILS_EXIT_CRITICAL_SECTION() FURI_CRITICAL_EXIT() - -#define UTILS_MEMSET8(dest, value, size) memset(dest, value, size); - -/****************************************************************************** - * tiny low power manager - * (any macro that does not need to be modified can be removed) - ******************************************************************************/ -#define UTIL_LPM_INIT_CRITICAL_SECTION() -#define UTIL_LPM_ENTER_CRITICAL_SECTION() UTILS_ENTER_CRITICAL_SECTION() -#define UTIL_LPM_EXIT_CRITICAL_SECTION() UTILS_EXIT_CRITICAL_SECTION() - -/****************************************************************************** - * sequencer - * (any macro that does not need to be modified can be removed) - ******************************************************************************/ -#define UTIL_SEQ_INIT_CRITICAL_SECTION() -#define UTIL_SEQ_ENTER_CRITICAL_SECTION() UTILS_ENTER_CRITICAL_SECTION() -#define UTIL_SEQ_EXIT_CRITICAL_SECTION() UTILS_EXIT_CRITICAL_SECTION() -#define UTIL_SEQ_CONF_TASK_NBR (32) -#define UTIL_SEQ_CONF_PRIO_NBR (2) -#define UTIL_SEQ_MEMSET8(dest, value, size) UTILS_MEMSET8(dest, value, size) - -#ifdef __cplusplus -} -#endif - -#endif /*UTILITIES_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/firmware/targets/f7/furi_hal/furi_hal_bt.c b/firmware/targets/f7/furi_hal/furi_hal_bt.c index 57aee0bf2..34818e569 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_bt.c +++ b/firmware/targets/f7/furi_hal/furi_hal_bt.c @@ -2,7 +2,11 @@ #include #include + #include +#include + +#include #include #include diff --git a/firmware/targets/f7/furi_hal/furi_hal_clock.c b/firmware/targets/f7/furi_hal/furi_hal_clock.c index 736ad9f7c..86c8fd467 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_clock.c +++ b/firmware/targets/f7/furi_hal/furi_hal_clock.c @@ -4,19 +4,26 @@ #include #include +#include #include #include +#include +#include + #define TAG "FuriHalClock" -#define CPU_CLOCK_HZ_EARLY 4000000 -#define CPU_CLOCK_HZ_MAIN 64000000 +#define CPU_CLOCK_EARLY_HZ 4000000 +#define CPU_CLOCK_HSI16_HZ 16000000 +#define CPU_CLOCK_HSE_HZ 32000000 +#define CPU_CLOCK_PLL_HZ 64000000 + #define TICK_INT_PRIORITY 15U #define HS_CLOCK_IS_READY() (LL_RCC_HSE_IsReady() && LL_RCC_HSI_IsReady()) #define LS_CLOCK_IS_READY() (LL_RCC_LSE_IsReady() && LL_RCC_LSI1_IsReady()) void furi_hal_clock_init_early() { - LL_SetSystemCoreClock(CPU_CLOCK_HZ_EARLY); + LL_SetSystemCoreClock(CPU_CLOCK_EARLY_HZ); LL_Init1msTick(SystemCoreClock); } @@ -24,11 +31,6 @@ void furi_hal_clock_deinit_early() { } void furi_hal_clock_init() { - /* Prepare Flash memory for 64MHz system clock */ - LL_FLASH_SetLatency(LL_FLASH_LATENCY_3); - while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3) - ; - /* HSE and HSI configuration and activation */ LL_RCC_HSE_SetCapacitorTuning(0x26); LL_RCC_HSE_Enable(); @@ -49,9 +51,6 @@ void furi_hal_clock_init() { while(!LS_CLOCK_IS_READY()) ; - /* RF wakeup */ - LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE); - LL_EXTI_EnableIT_0_31( LL_EXTI_LINE_18); /* Why? Because that's why. See RM0434, Table 61. CPU1 vector table. */ LL_EXTI_EnableRisingTrig_0_31(LL_EXTI_LINE_18); @@ -79,12 +78,17 @@ void furi_hal_clock_init() { ; /* Sysclk activation on the main PLL */ - /* Set CPU1 prescaler*/ + /* Set CPU1 prescaler */ LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - /* Set CPU2 prescaler*/ + /* Set CPU2 prescaler, from this point we are not allowed to touch it. */ LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); + /* Prepare Flash memory for work on 64MHz system clock */ + LL_FLASH_SetLatency(LL_FLASH_LATENCY_3); + while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3) + ; + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) ; @@ -104,7 +108,7 @@ void furi_hal_clock_init() { ; /* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */ - LL_SetSystemCoreClock(CPU_CLOCK_HZ_MAIN); + LL_SetSystemCoreClock(CPU_CLOCK_PLL_HZ); /* Update the time base */ LL_Init1msTick(SystemCoreClock); @@ -122,7 +126,7 @@ void furi_hal_clock_init() { FURI_LOG_I(TAG, "Init OK"); } -void furi_hal_clock_switch_to_hsi() { +void furi_hal_clock_switch_hse2hsi() { LL_RCC_HSI_Enable(); while(!LL_RCC_HSI_IsReady()) @@ -134,38 +138,27 @@ void furi_hal_clock_switch_to_hsi() { while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) ; - LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); - LL_FLASH_SetLatency(LL_FLASH_LATENCY_0); while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_0) ; } -void furi_hal_clock_switch_to_pll() { +void furi_hal_clock_switch_hsi2hse() { #ifdef FURI_HAL_CLOCK_TRACK_STARTUP uint32_t clock_start_time = DWT->CYCCNT; #endif LL_RCC_HSE_Enable(); - LL_RCC_PLL_Enable(); - LL_RCC_PLLSAI1_Enable(); - while(!LL_RCC_HSE_IsReady()) ; - while(!LL_RCC_PLL_IsReady()) - ; - while(!LL_RCC_PLLSAI1_IsReady()) + + LL_FLASH_SetLatency(LL_FLASH_LATENCY_1); + while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1) ; - LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE); - LL_FLASH_SetLatency(LL_FLASH_LATENCY_3); - while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3) - ; - - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - - while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) ; #ifdef FURI_HAL_CLOCK_TRACK_STARTUP @@ -176,6 +169,48 @@ void furi_hal_clock_switch_to_pll() { #endif } +bool furi_hal_clock_switch_hse2pll() { + furi_assert(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSE); + + LL_RCC_PLL_Enable(); + LL_RCC_PLLSAI1_Enable(); + + while(!LL_RCC_PLL_IsReady()) + ; + while(!LL_RCC_PLLSAI1_IsReady()) + ; + + if(SHCI_C2_SetSystemClock(SET_SYSTEM_CLOCK_HSE_TO_PLL) != SHCI_Success) { + return false; + } + + furi_check(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL); + + LL_SetSystemCoreClock(CPU_CLOCK_PLL_HZ); + SysTick->LOAD = (uint32_t)((SystemCoreClock / 1000) - 1UL); + + return true; +} + +bool furi_hal_clock_switch_pll2hse() { + furi_assert(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL); + + LL_RCC_HSE_Enable(); + while(!LL_RCC_HSE_IsReady()) + ; + + if(SHCI_C2_SetSystemClock(SET_SYSTEM_CLOCK_PLL_ON_TO_HSE) != SHCI_Success) { + return false; + } + + furi_check(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSE); + + LL_SetSystemCoreClock(CPU_CLOCK_HSE_HZ); + SysTick->LOAD = (uint32_t)((SystemCoreClock / 1000) - 1UL); + + return true; +} + void furi_hal_clock_suspend_tick() { CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_ENABLE_Msk); } diff --git a/firmware/targets/f7/furi_hal/furi_hal_clock.h b/firmware/targets/f7/furi_hal/furi_hal_clock.h index 5e651bbd3..3100b619f 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_clock.h +++ b/firmware/targets/f7/furi_hal/furi_hal_clock.h @@ -1,11 +1,12 @@ #pragma once +#include +#include + #ifdef __cplusplus extern "C" { #endif -#include - typedef enum { FuriHalClockMcoLse, FuriHalClockMcoSysclk, @@ -40,11 +41,23 @@ void furi_hal_clock_deinit_early(); /** Initialize clocks */ void furi_hal_clock_init(); -/** Switch to HSI clock */ -void furi_hal_clock_switch_to_hsi(); +/** Switch clock from HSE to HSI */ +void furi_hal_clock_switch_hse2hsi(); -/** Switch to PLL clock */ -void furi_hal_clock_switch_to_pll(); +/** Switch clock from HSI to HSE */ +void furi_hal_clock_switch_hsi2hse(); + +/** Switch clock from HSE to PLL + * + * @return true if changed, false if failed or not possible at this moment + */ +bool furi_hal_clock_switch_hse2pll(); + +/** Switch clock from PLL to HSE + * + * @return true if changed, false if failed or not possible at this moment + */ +bool furi_hal_clock_switch_pll2hse(); /** Stop SysTick counter without resetting */ void furi_hal_clock_suspend_tick(); diff --git a/firmware/targets/f7/furi_hal/furi_hal_console.c b/firmware/targets/f7/furi_hal/furi_hal_console.c index 2bdc57250..0b113d2da 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_console.c +++ b/firmware/targets/f7/furi_hal/furi_hal_console.c @@ -5,8 +5,6 @@ #include #include -#include - #include #define TAG "FuriHalConsole" diff --git a/firmware/targets/f7/furi_hal/furi_hal_flash.c b/firmware/targets/f7/furi_hal/furi_hal_flash.c index 796d20b19..bc65b29eb 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_flash.c +++ b/firmware/targets/f7/furi_hal/furi_hal_flash.c @@ -7,6 +7,9 @@ #include #include +#include + +#include #define TAG "FuriHalFlash" diff --git a/firmware/targets/f7/furi_hal/furi_hal_memory.c b/firmware/targets/f7/furi_hal/furi_hal_memory.c index 7f69b90ca..3f8df1f44 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_memory.c +++ b/firmware/targets/f7/furi_hal/furi_hal_memory.c @@ -4,9 +4,6 @@ #define TAG "FuriHalMemory" -// STM(TM) Copro(TM) bug(TM) workaround size -#define RAM2B_COPRO_GAP_SIZE_KB 2 - typedef enum { SRAM_A, SRAM_B, @@ -38,13 +35,20 @@ void furi_hal_memory_init() { uint32_t sbrsa = (FLASH->SRRVR & FLASH_SRRVR_SBRSA_Msk) >> FLASH_SRRVR_SBRSA_Pos; uint32_t snbrsa = (FLASH->SRRVR & FLASH_SRRVR_SNBRSA_Msk) >> FLASH_SRRVR_SNBRSA_Pos; + // STM(TM) Copro(TM) bug(TM): SNBRSA is incorrect if stack version is higher than 1.13 and lower than 1.17.2+ + // Radio core started, but not yet ready, so we'll try to guess + // This will be true only if BLE light radio stack used, + // 0x0D is known to be incorrect, 0x0B is known to be correct since 1.17.2+ + // Lower value by 2 pages to match real memory layout + if(snbrsa > 0x0B) { + FURI_LOG_E(TAG, "SNBRSA workaround"); + snbrsa -= 2; + } + uint32_t sram2a_busy_size = (uint32_t)&__sram2a_free__ - (uint32_t)&__sram2a_start__; uint32_t sram2a_unprotected_size = (sbrsa)*1024; uint32_t sram2b_unprotected_size = (snbrsa)*1024; - // STM(TM) Copro(TM) bug(TM) workaround - sram2b_unprotected_size -= 1024 * RAM2B_COPRO_GAP_SIZE_KB; - memory->region[SRAM_A].start = (uint8_t*)&__sram2a_free__; memory->region[SRAM_B].start = (uint8_t*)&__sram2b_start__; diff --git a/firmware/targets/f7/furi_hal/furi_hal_os.c b/firmware/targets/f7/furi_hal/furi_hal_os.c index 3fc1fbea8..046cf79dc 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_os.c +++ b/firmware/targets/f7/furi_hal/furi_hal_os.c @@ -170,27 +170,35 @@ void vPortSuppressTicksAndSleep(TickType_t expected_idle_ticks) { return; } + // Core2 shenanigans takes extra time, so we want to compensate tick skew by reducing sleep duration by 1 tick + TickType_t unexpected_idle_ticks = expected_idle_ticks - 1; + // Limit amount of ticks to maximum that timer can count - if(expected_idle_ticks > FURI_HAL_OS_MAX_SLEEP) { - expected_idle_ticks = FURI_HAL_OS_MAX_SLEEP; + if(unexpected_idle_ticks > FURI_HAL_OS_MAX_SLEEP) { + unexpected_idle_ticks = FURI_HAL_OS_MAX_SLEEP; } // Stop IRQ handling, no one should disturb us till we finish __disable_irq(); + do { + // Confirm OS that sleep is still possible + if(eTaskConfirmSleepModeStatus() == eAbortSleep || furi_hal_os_is_pending_irq()) { + break; + } - // Confirm OS that sleep is still possible - if(eTaskConfirmSleepModeStatus() == eAbortSleep || furi_hal_os_is_pending_irq()) { - __enable_irq(); - return; - } - - // Sleep and track how much ticks we spent sleeping - uint32_t completed_ticks = furi_hal_os_sleep(expected_idle_ticks); - // Notify system about time spent in sleep - if(completed_ticks > 0) { - vTaskStepTick(MIN(completed_ticks, expected_idle_ticks)); - } - + // Sleep and track how much ticks we spent sleeping + uint32_t completed_ticks = furi_hal_os_sleep(unexpected_idle_ticks); + // Notify system about time spent in sleep + if(completed_ticks > 0) { + if(completed_ticks > expected_idle_ticks) { +#ifdef FURI_HAL_OS_DEBUG + furi_hal_console_printf(">%lu\r\n", completed_ticks - expected_idle_ticks); +#endif + completed_ticks = expected_idle_ticks; + } + vTaskStepTick(completed_ticks); + } + } while(0); // Reenable IRQ __enable_irq(); } diff --git a/firmware/targets/f7/furi_hal/furi_hal_power.c b/firmware/targets/f7/furi_hal/furi_hal_power.c index 035919d78..c14de8569 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_power.c +++ b/firmware/targets/f7/furi_hal/furi_hal_power.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include #include #include @@ -162,6 +162,11 @@ static inline void furi_hal_power_resume_aux_periphs() { static inline void furi_hal_power_deep_sleep() { furi_hal_power_suspend_aux_periphs(); + if(!furi_hal_clock_switch_pll2hse()) { + // Hello core2 my old friend + return; + } + while(LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) ; @@ -171,13 +176,13 @@ static inline void furi_hal_power_deep_sleep() { LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0); // The switch on HSI before entering Stop Mode is required - furi_hal_clock_switch_to_hsi(); + furi_hal_clock_switch_hse2hsi(); } } else { /** * The switch on HSI before entering Stop Mode is required */ - furi_hal_clock_switch_to_hsi(); + furi_hal_clock_switch_hse2hsi(); } /* Release RCC semaphore */ @@ -201,12 +206,14 @@ static inline void furi_hal_power_deep_sleep() { while(LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) ; - if(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) { - furi_hal_clock_switch_to_pll(); + if(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) { + furi_hal_clock_switch_hsi2hse(); } LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0); + furi_check(furi_hal_clock_switch_hse2pll()); + furi_hal_power_resume_aux_periphs(); furi_hal_rtc_sync_shadow(); } diff --git a/firmware/targets/f7/furi_hal/furi_hal_random.c b/firmware/targets/f7/furi_hal/furi_hal_random.c index cf4b552f6..225519303 100644 --- a/firmware/targets/f7/furi_hal/furi_hal_random.c +++ b/firmware/targets/f7/furi_hal/furi_hal_random.c @@ -6,7 +6,7 @@ #include #include -#include +#include #define TAG "FuriHalRandom" diff --git a/lib/stm32wb.scons b/lib/stm32wb.scons index 94a1c7075..8a8ad9644 100644 --- a/lib/stm32wb.scons +++ b/lib/stm32wb.scons @@ -64,7 +64,6 @@ sources += [ "stm32wb_copro/wpan/ble/core/auto/ble_l2cap_aci.c", "stm32wb_copro/wpan/ble/core/template/osal.c", "stm32wb_copro/wpan/utilities/dbg_trace.c", - "stm32wb_copro/wpan/utilities/otp.c", "stm32wb_copro/wpan/utilities/stm_list.c", ] diff --git a/lib/stm32wb_copro b/lib/stm32wb_copro index 6c9c54f05..bbccbefae 160000 --- a/lib/stm32wb_copro +++ b/lib/stm32wb_copro @@ -1 +1 @@ -Subproject commit 6c9c54f05669b2c4d436df58bb691d3b0d7c86df +Subproject commit bbccbefae26a2301b8a4b58e57ebdeb93c08269b diff --git a/scripts/ob.data b/scripts/ob.data index 605faccbf..9f6f1d081 100644 --- a/scripts/ob.data +++ b/scripts/ob.data @@ -14,15 +14,15 @@ IWDGSTOP:0x1:rw IWDGSW:0x1:rw IPCCDBA:0x0:rw ESE:0x1:r -SFSA:0xD5:r +SFSA:0xD7:r FSD:0x0:r DDS:0x1:r C2OPT:0x1:r NBRSD:0x0:r -SNBRSA:0xD:r +SNBRSA:0xB:r BRSD:0x0:r SBRSA:0x12:r -SBRV:0x35400:r +SBRV:0x35C00:r PCROP1A_STRT:0x1FF:r PCROP1A_END:0x0:r PCROP_RDP:0x1:rw diff --git a/scripts/update.py b/scripts/update.py index 9f0d95d94..c315ef8ad 100755 --- a/scripts/update.py +++ b/scripts/update.py @@ -73,6 +73,9 @@ class Main(App): self.parser_generate.add_argument( "--I-understand-what-I-am-doing", dest="disclaimer", required=False ) + self.parser_generate.add_argument( + "--stackversion", dest="stack_version", required=False, default="" + ) self.parser_generate.set_defaults(func=self.generate) @@ -93,6 +96,13 @@ class Main(App): if not self.args.radiotype: raise ValueError("Missing --radiotype") radio_meta = CoproBinary(self.args.radiobin) + if self.args.stack_version: + actual_stack_version_str = f"{radio_meta.img_sig.version_major}.{radio_meta.img_sig.version_minor}.{radio_meta.img_sig.version_sub}" + if actual_stack_version_str != self.args.stack_version: + self.logger.error( + f"Stack version mismatch: expected {self.args.stack_version}, actual {actual_stack_version_str}" + ) + return 1 radio_version = self.copro_version_as_int(radio_meta, self.args.radiotype) if ( get_stack_type(self.args.radiotype) not in self.WHITELISTED_STACK_TYPES