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https://github.com/DarkFlippers/unleashed-firmware.git
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Github: fix non zero return behavior in docker actions. Firmware: fix F6 build. (#886)
* Github: treat non 0 exit code as fatal * GitHub: inject missing -e flag to bash in docker * Firmware: sync targets
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2
.github/workflows/build.yml
vendored
2
.github/workflows/build.yml
vendored
@ -82,6 +82,7 @@ jobs:
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uses: ./.github/actions/docker
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with:
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run: |
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set -e
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for TARGET in ${TARGETS}
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do
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make TARGET=${TARGET}
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@ -92,6 +93,7 @@ jobs:
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uses: ./.github/actions/docker
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with:
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run: |
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set -e
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for TARGET in ${TARGETS}
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do
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mv dist/${TARGET}/* artifacts/
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@ -4,6 +4,7 @@
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#include <stdbool.h>
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#define SERIAL_SVC_DATA_LEN_MAX (486)
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#define SERIAL_SVC_CHAR_VALUE_LEN_MAX (243)
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#ifdef __cplusplus
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extern "C" {
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@ -296,9 +296,9 @@ static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
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{CC1101_IOCFG0, 0x06}, //GDO0 Output Pin Configuration
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{CC1101_FIFOTHR, 0x47}, //RX FIFO and TX FIFO Thresholds
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//1 : CRC calculation in TX and CRC check in RX enabled,
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//1 : CRC calculation in TX and CRC check in RX enabled,
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//1 : Variable packet length mode. Packet length configured by the first byte after sync word
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{CC1101_PKTCTRL0, 0x05},
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{CC1101_PKTCTRL0,0x05},
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{CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control
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@ -314,8 +314,8 @@ static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
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{CC1101_DEVIATN, 0x34}, //Deviation = 19.042969
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{CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration
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{CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration
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{CC1101_AGCCTRL2, 0x43}, //AGC Control
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{CC1101_AGCCTRL2, 0x43 }, //AGC Control
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{CC1101_AGCCTRL1, 0x40},
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{CC1101_AGCCTRL0, 0x91},
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@ -392,8 +392,7 @@ void furi_hal_subghz_init() {
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;
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// GD0 high
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cc1101_write_reg(
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&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
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cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
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while(hal_gpio_read(&gpio_cc1101_g0) != true)
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;
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@ -454,7 +453,7 @@ void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
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} else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) {
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furi_hal_subghz_load_registers(furi_hal_subghz_preset_gfsk_9_99kb_async_regs);
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furi_hal_subghz_load_patable(furi_hal_subghz_preset_gfsk_async_patable);
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} else {
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} else{
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furi_crash(NULL);
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}
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}
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@ -499,8 +498,7 @@ void furi_hal_subghz_flush_tx() {
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bool furi_hal_subghz_rx_pipe_not_empty() {
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CC1101RxBytes status[1];
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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cc1101_read_reg(
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&furi_hal_spi_bus_handle_subghz, (CC1101_STATUS_RXBYTES) | CC1101_BURST, (uint8_t*)status);
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cc1101_read_reg(&furi_hal_spi_bus_handle_subghz, (CC1101_STATUS_RXBYTES) | CC1101_BURST, (uint8_t*)status);
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furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
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// TODO: you can add a buffer overflow flag if needed
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if(status->NUM_RXBYTES > 0) {
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@ -674,15 +672,13 @@ void furi_hal_subghz_set_path(FuriHalSubGhzPath path) {
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furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
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if(path == FuriHalSubGhzPath433) {
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hal_gpio_write(&gpio_rf_sw_0, 0);
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cc1101_write_reg(
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&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
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cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
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} else if(path == FuriHalSubGhzPath315) {
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hal_gpio_write(&gpio_rf_sw_0, 1);
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cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW);
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} else if(path == FuriHalSubGhzPath868) {
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hal_gpio_write(&gpio_rf_sw_0, 1);
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cc1101_write_reg(
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&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
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cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
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} else if(path == FuriHalSubGhzPathIsolate) {
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hal_gpio_write(&gpio_rf_sw_0, 0);
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cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW);
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@ -74,4 +74,4 @@ void furi_hal_uart_set_irq_cb(
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#ifdef __cplusplus
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}
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#endif
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#endif
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