mirror of
https://github.com/DarkFlippers/unleashed-firmware.git
synced 2024-12-15 00:33:05 +03:00
316 lines
8.0 KiB
C
316 lines
8.0 KiB
C
#include "furi_hal_interrupt.h"
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#include "furi_hal_os.h"
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#include <furi.h>
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#include <stm32wbxx.h>
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#include <stm32wbxx_ll_tim.h>
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#include <stm32wbxx_ll_rcc.h>
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#include <stm32wbxx_ll_cortex.h>
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#define TAG "FuriHalInterrupt"
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#define FURI_HAL_INTERRUPT_DEFAULT_PRIORITY 5
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typedef struct {
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FuriHalInterruptISR isr;
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void* context;
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} FuriHalInterruptISRPair;
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FuriHalInterruptISRPair furi_hal_interrupt_isr[FuriHalInterruptIdMax] = {0};
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const IRQn_Type furi_hal_interrupt_irqn[FuriHalInterruptIdMax] = {
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// TIM1, TIM16, TIM17
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[FuriHalInterruptIdTim1TrgComTim17] = TIM1_TRG_COM_TIM17_IRQn,
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[FuriHalInterruptIdTim1Cc] = TIM1_CC_IRQn,
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[FuriHalInterruptIdTim1UpTim16] = TIM1_UP_TIM16_IRQn,
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// TIM2
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[FuriHalInterruptIdTIM2] = TIM2_IRQn,
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// DMA1
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[FuriHalInterruptIdDma1Ch1] = DMA1_Channel1_IRQn,
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[FuriHalInterruptIdDma1Ch2] = DMA1_Channel2_IRQn,
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[FuriHalInterruptIdDma1Ch3] = DMA1_Channel3_IRQn,
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[FuriHalInterruptIdDma1Ch4] = DMA1_Channel4_IRQn,
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[FuriHalInterruptIdDma1Ch5] = DMA1_Channel5_IRQn,
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[FuriHalInterruptIdDma1Ch6] = DMA1_Channel6_IRQn,
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[FuriHalInterruptIdDma1Ch7] = DMA1_Channel7_IRQn,
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// DMA2
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[FuriHalInterruptIdDma2Ch1] = DMA2_Channel1_IRQn,
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[FuriHalInterruptIdDma2Ch2] = DMA2_Channel2_IRQn,
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[FuriHalInterruptIdDma2Ch3] = DMA2_Channel3_IRQn,
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[FuriHalInterruptIdDma2Ch4] = DMA2_Channel4_IRQn,
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[FuriHalInterruptIdDma2Ch5] = DMA2_Channel5_IRQn,
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[FuriHalInterruptIdDma2Ch6] = DMA2_Channel6_IRQn,
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[FuriHalInterruptIdDma2Ch7] = DMA2_Channel7_IRQn,
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// RCC
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[FuriHalInterruptIdRcc] = RCC_IRQn,
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// COMP
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[FuriHalInterruptIdCOMP] = COMP_IRQn,
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// HSEM
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[FuriHalInterruptIdHsem] = HSEM_IRQn,
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// LPTIMx
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[FuriHalInterruptIdLpTim1] = LPTIM1_IRQn,
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[FuriHalInterruptIdLpTim2] = LPTIM2_IRQn,
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};
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__attribute__((always_inline)) static inline void
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furi_hal_interrupt_call(FuriHalInterruptId index) {
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furi_assert(furi_hal_interrupt_isr[index].isr);
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furi_hal_interrupt_isr[index].isr(furi_hal_interrupt_isr[index].context);
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}
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__attribute__((always_inline)) static inline void
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furi_hal_interrupt_enable(FuriHalInterruptId index, uint16_t priority) {
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NVIC_SetPriority(
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furi_hal_interrupt_irqn[index],
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), priority, 0));
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NVIC_EnableIRQ(furi_hal_interrupt_irqn[index]);
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}
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__attribute__((always_inline)) static inline void
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furi_hal_interrupt_disable(FuriHalInterruptId index) {
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NVIC_DisableIRQ(furi_hal_interrupt_irqn[index]);
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}
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void furi_hal_interrupt_init() {
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NVIC_SetPriority(
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TAMP_STAMP_LSECSS_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 0, 0));
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NVIC_EnableIRQ(TAMP_STAMP_LSECSS_IRQn);
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NVIC_SetPriority(PendSV_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
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NVIC_SetPriority(FPU_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 15, 0));
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NVIC_EnableIRQ(FPU_IRQn);
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LL_SYSCFG_DisableIT_FPU_IOC();
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LL_SYSCFG_DisableIT_FPU_DZC();
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LL_SYSCFG_DisableIT_FPU_UFC();
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LL_SYSCFG_DisableIT_FPU_OFC();
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LL_SYSCFG_DisableIT_FPU_IDC();
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LL_SYSCFG_DisableIT_FPU_IXC();
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LL_HANDLER_EnableFault(LL_HANDLER_FAULT_USG);
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LL_HANDLER_EnableFault(LL_HANDLER_FAULT_BUS);
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LL_HANDLER_EnableFault(LL_HANDLER_FAULT_MEM);
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FURI_LOG_I(TAG, "Init OK");
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}
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void furi_hal_interrupt_set_isr(FuriHalInterruptId index, FuriHalInterruptISR isr, void* context) {
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furi_hal_interrupt_set_isr_ex(index, FURI_HAL_INTERRUPT_DEFAULT_PRIORITY, isr, context);
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}
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void furi_hal_interrupt_set_isr_ex(
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FuriHalInterruptId index,
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uint16_t priority,
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FuriHalInterruptISR isr,
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void* context) {
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furi_assert(index < FuriHalInterruptIdMax);
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furi_assert(priority < 15);
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furi_assert(furi_hal_interrupt_irqn[index]);
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if(isr) {
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// Pre ISR set
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furi_assert(furi_hal_interrupt_isr[index].isr == NULL);
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} else {
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// Pre ISR clear
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furi_assert(furi_hal_interrupt_isr[index].isr != NULL);
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furi_hal_interrupt_disable(index);
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}
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furi_hal_interrupt_isr[index].isr = isr;
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furi_hal_interrupt_isr[index].context = context;
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__DMB();
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if(isr) {
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// Post ISR set
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furi_hal_interrupt_enable(index, priority);
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} else {
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// Post ISR clear
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}
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}
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/* Timer 2 */
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void TIM2_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdTIM2);
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}
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/* Timer 1 Update */
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void TIM1_UP_TIM16_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdTim1UpTim16);
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}
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void TIM1_TRG_COM_TIM17_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdTim1TrgComTim17);
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}
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void TIM1_CC_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdTim1Cc);
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}
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/* DMA 1 */
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void DMA1_Channel1_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch1);
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}
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void DMA1_Channel2_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch2);
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}
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void DMA1_Channel3_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch3);
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}
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void DMA1_Channel4_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch4);
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}
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void DMA1_Channel5_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch5);
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}
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void DMA1_Channel6_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch6);
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}
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void DMA1_Channel7_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma1Ch7);
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}
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/* DMA 2 */
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void DMA2_Channel1_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch1);
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}
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void DMA2_Channel2_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch2);
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}
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void DMA2_Channel3_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch3);
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}
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void DMA2_Channel4_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch4);
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}
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void DMA2_Channel5_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch5);
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}
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void DMA2_Channel6_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch6);
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}
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void DMA2_Channel7_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdDma2Ch7);
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}
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void HSEM_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdHsem);
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}
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void TAMP_STAMP_LSECSS_IRQHandler(void) {
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if(LL_RCC_IsActiveFlag_LSECSS()) {
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LL_RCC_ClearFlag_LSECSS();
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if(!LL_RCC_LSE_IsReady()) {
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FURI_LOG_E(TAG, "LSE CSS fired: resetting system");
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NVIC_SystemReset();
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} else {
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FURI_LOG_E(TAG, "LSE CSS fired: but LSE is alive");
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}
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}
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}
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void RCC_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdRcc);
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}
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void NMI_Handler() {
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if(LL_RCC_IsActiveFlag_HSECSS()) {
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LL_RCC_ClearFlag_HSECSS();
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FURI_LOG_E(TAG, "HSE CSS fired: resetting system");
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NVIC_SystemReset();
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}
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}
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void HardFault_Handler() {
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furi_crash("HardFault");
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}
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void MemManage_Handler() {
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if(FURI_BIT(SCB->CFSR, SCB_CFSR_MMARVALID_Pos)) {
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uint32_t memfault_address = SCB->MMFAR;
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if(memfault_address < (1024 * 1024)) {
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// from 0x00 to 1MB, see FuriHalMpuRegionNULL
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furi_crash("NULL pointer dereference");
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} else {
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// write or read of MPU region 1 (FuriHalMpuRegionStack)
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furi_crash("MPU fault, possibly stack overflow");
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}
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} else if(FURI_BIT(SCB->CFSR, SCB_CFSR_MSTKERR_Pos)) {
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// push to stack on MPU region 1 (FuriHalMpuRegionStack)
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furi_crash("MemManage fault, possibly stack overflow");
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}
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furi_crash("MemManage");
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}
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void BusFault_Handler() {
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furi_crash("BusFault");
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}
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void UsageFault_Handler() {
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furi_crash("UsageFault");
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}
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void DebugMon_Handler() {
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}
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#include "usbd_core.h"
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extern usbd_device udev;
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extern void HW_IPCC_Tx_Handler();
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extern void HW_IPCC_Rx_Handler();
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void SysTick_Handler() {
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furi_hal_os_tick();
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}
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void USB_LP_IRQHandler() {
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#ifndef FURI_RAM_EXEC
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usbd_poll(&udev);
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#endif
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}
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void USB_HP_IRQHandler() {
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}
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void IPCC_C1_TX_IRQHandler() {
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HW_IPCC_Tx_Handler();
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}
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void IPCC_C1_RX_IRQHandler() {
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HW_IPCC_Rx_Handler();
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}
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void FPU_IRQHandler() {
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furi_crash("FpuFault");
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}
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void LPTIM1_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdLpTim1);
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}
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void LPTIM2_IRQHandler() {
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furi_hal_interrupt_call(FuriHalInterruptIdLpTim2);
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}
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