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https://github.com/DarkFlippers/unleashed-firmware.git
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917410a0a8
* fbt: reworking targets & assets handling WIP * fbt: dist fixes * fbt: moved SD card resources to owning apps * unit_tests: moved resources to app folder * github: updated unit_tests paths * github: packaging fixes * unit_tests: fixes * fbt: assets: internal cleanup * fbt: reworked assets handling * github: unit_tests: reintroducing fixes * minor cleanup * fbt: naming changes to reflect private nature of scons tools * fbt: resources: fixed dist archive paths * docs: updated paths * docs: updated more paths * docs: included "resources" parameter in app manifest docs; updated assets readme * updated gitignore for assets * github: updated action versions * unit_tests: restored timeout; scripts: assets: logging changes * gh: don't upload desktop animations for unit test run Co-authored-by: あく <alleteam@gmail.com>
82 lines
4.4 KiB
C
82 lines
4.4 KiB
C
#pragma once
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/******************************************************************************
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* Semaphores
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* THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
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*****************************************************************************/
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/**
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* Index of the semaphore used the prevent conflicts after standby sleep.
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* Each CPUs takes this semaphore at standby wakeup until conflicting elements are restored.
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*/
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#define CFG_HW_PWR_STANDBY_SEMID 10
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/**
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* The CPU2 may be configured to store the Thread persistent data either in internal NVM storage on CPU2 or in
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* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config()
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* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed.
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* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be:
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* + CPU1 takes CFG_HW_THREAD_NVM_SRAM_SEMID semaphore
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* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1)
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* + CPU1 releases CFG_HW_THREAD_NVM_SRAM_SEMID semaphore
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* CFG_HW_THREAD_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them.
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* There is no timing constraint on how long this semaphore can be kept.
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*/
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#define CFG_HW_THREAD_NVM_SRAM_SEMID 9
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/**
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* The CPU2 may be configured to store the BLE persistent data either in internal NVM storage on CPU2 or in
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* SRAM2 buffer provided by the user application. This can be configured with the system command SHCI_C2_Config()
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* When the CPU2 is requested to store persistent data in SRAM2, it can write data in this buffer at any time when needed.
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* In order to read consistent data with the CPU1 from the SRAM2 buffer, the flow should be:
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* + CPU1 takes CFG_HW_BLE_NVM_SRAM_SEMID semaphore
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* + CPU1 reads all persistent data from SRAM2 (most of the time, the goal is to write these data into an NVM managed by CPU1)
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* + CPU1 releases CFG_HW_BLE_NVM_SRAM_SEMID semaphore
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* CFG_HW_BLE_NVM_SRAM_SEMID semaphore makes sure CPU2 does not update the persistent data in SRAM2 at the same time CPU1 is reading them.
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* There is no timing constraint on how long this semaphore can be kept.
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*/
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#define CFG_HW_BLE_NVM_SRAM_SEMID 8
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/**
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* Index of the semaphore used by CPU2 to prevent the CPU1 to either write or erase data in flash
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* The CPU1 shall not either write or erase in flash when this semaphore is taken by the CPU2
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* When the CPU1 needs to either write or erase in flash, it shall first get the semaphore and release it just
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* after writing a raw (64bits data) or erasing one sector.
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* Once the Semaphore has been released, there shall be at least 1us before it can be taken again. This is required
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* to give the opportunity to CPU2 to take it.
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* On v1.4.0 and older CPU2 wireless firmware, this semaphore is unused and CPU2 is using PES bit.
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* By default, CPU2 is using the PES bit to protect its timing. The CPU1 may request the CPU2 to use the semaphore
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* instead of the PES bit by sending the system command SHCI_C2_SetFlashActivityControl()
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*/
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#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID 7
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/**
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* Index of the semaphore used by CPU1 to prevent the CPU2 to either write or erase data in flash
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* In order to protect its timing, the CPU1 may get this semaphore to prevent the CPU2 to either
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* write or erase in flash (as this will stall both CPUs)
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* The PES bit shall not be used as this may stall the CPU2 in some cases.
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*/
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#define CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID 6
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/**
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* Index of the semaphore used to manage the CLK48 clock configuration
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* When the USB is required, this semaphore shall be taken before configuring te CLK48 for USB
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* and should be released after the application switch OFF the clock when the USB is not used anymore
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* When using the RNG, it is good enough to use CFG_HW_RNG_SEMID to control CLK48.
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* More details in AN5289
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*/
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#define CFG_HW_CLK48_CONFIG_SEMID 5
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/* Index of the semaphore used to manage the entry Stop Mode procedure */
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#define CFG_HW_ENTRY_STOP_MODE_SEMID 4
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/* Index of the semaphore used to access the RCC */
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#define CFG_HW_RCC_SEMID 3
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/* Index of the semaphore used to access the FLASH */
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#define CFG_HW_FLASH_SEMID 2
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/* Index of the semaphore used to access the PKA */
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#define CFG_HW_PKA_SEMID 1
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/* Index of the semaphore used to access the RNG */
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#define CFG_HW_RNG_SEMID 0
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