mirror of
https://github.com/DarkFlippers/unleashed-firmware.git
synced 2024-12-02 03:02:28 +03:00
356 lines
12 KiB
C
356 lines
12 KiB
C
#include "furi_hal_nfc_i.h"
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#include "furi_hal_nfc_tech_i.h"
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#include <furi.h>
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#include <furi_hal_resources.h>
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#include <digital_signal/presets/nfc/iso14443_3a_signal.h>
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#define TAG "FuriHalIso14443a"
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// Prevent FDT timer from starting
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#define FURI_HAL_NFC_ISO14443A_LISTENER_FDT_COMP_FC (INT32_MAX)
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static Iso14443_3aSignal* iso14443_3a_signal = NULL;
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static FuriHalNfcError furi_hal_nfc_iso14443a_common_init(FuriHalSpiBusHandle* handle) {
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// Common NFC-A settings, 106 kbps
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// 1st stage zero = 600kHz, 3rd stage zero = 200 kHz
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st25r3916_write_reg(handle, ST25R3916_REG_RX_CONF1, ST25R3916_REG_RX_CONF1_z600k);
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// AGC enabled, ratio 3:1, squelch after TX
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st25r3916_write_reg(
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handle,
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ST25R3916_REG_RX_CONF2,
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ST25R3916_REG_RX_CONF2_agc6_3 | ST25R3916_REG_RX_CONF2_agc_m |
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ST25R3916_REG_RX_CONF2_agc_en | ST25R3916_REG_RX_CONF2_sqm_dyn);
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// HF operation, full gain on AM and PM channels
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st25r3916_write_reg(handle, ST25R3916_REG_RX_CONF3, 0x00);
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// No gain reduction on AM and PM channels
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st25r3916_write_reg(handle, ST25R3916_REG_RX_CONF4, 0x00);
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// Correlator config
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st25r3916_write_reg(
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handle,
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ST25R3916_REG_CORR_CONF1,
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ST25R3916_REG_CORR_CONF1_corr_s0 | ST25R3916_REG_CORR_CONF1_corr_s4 |
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ST25R3916_REG_CORR_CONF1_corr_s6);
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// Sleep mode disable, 424kHz mode off
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st25r3916_write_reg(handle, ST25R3916_REG_CORR_CONF2, 0x00);
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return FuriHalNfcErrorNone;
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}
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static FuriHalNfcError furi_hal_nfc_iso14443a_poller_init(FuriHalSpiBusHandle* handle) {
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// Enable ISO14443A mode, OOK modulation
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_MODE,
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ST25R3916_REG_MODE_om_mask | ST25R3916_REG_MODE_tr_am,
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ST25R3916_REG_MODE_om_iso14443a | ST25R3916_REG_MODE_tr_am_ook);
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// Overshoot protection - is this necessary here?
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st25r3916_change_reg_bits(handle, ST25R3916_REG_OVERSHOOT_CONF1, 0xff, 0x40);
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st25r3916_change_reg_bits(handle, ST25R3916_REG_OVERSHOOT_CONF2, 0xff, 0x03);
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st25r3916_change_reg_bits(handle, ST25R3916_REG_UNDERSHOOT_CONF1, 0xff, 0x40);
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st25r3916_change_reg_bits(handle, ST25R3916_REG_UNDERSHOOT_CONF2, 0xff, 0x03);
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return furi_hal_nfc_iso14443a_common_init(handle);
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}
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static FuriHalNfcError furi_hal_nfc_iso14443a_poller_deinit(FuriHalSpiBusHandle* handle) {
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_ISO14443A_NFC,
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(ST25R3916_REG_ISO14443A_NFC_no_tx_par | ST25R3916_REG_ISO14443A_NFC_no_rx_par),
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(ST25R3916_REG_ISO14443A_NFC_no_tx_par_off | ST25R3916_REG_ISO14443A_NFC_no_rx_par_off));
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return FuriHalNfcErrorNone;
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}
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static FuriHalNfcError furi_hal_nfc_iso14443a_listener_init(FuriHalSpiBusHandle* handle) {
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furi_check(iso14443_3a_signal == NULL);
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iso14443_3a_signal = iso14443_3a_signal_alloc(&gpio_spi_r_mosi);
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st25r3916_write_reg(
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handle,
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ST25R3916_REG_OP_CONTROL,
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ST25R3916_REG_OP_CONTROL_en | ST25R3916_REG_OP_CONTROL_rx_en |
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ST25R3916_REG_OP_CONTROL_en_fd_auto_efd);
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st25r3916_write_reg(
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handle, ST25R3916_REG_MODE, ST25R3916_REG_MODE_targ_targ | ST25R3916_REG_MODE_om0);
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st25r3916_write_reg(
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handle,
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ST25R3916_REG_PASSIVE_TARGET,
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ST25R3916_REG_PASSIVE_TARGET_fdel_2 | ST25R3916_REG_PASSIVE_TARGET_fdel_0 |
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ST25R3916_REG_PASSIVE_TARGET_d_ac_ap2p | ST25R3916_REG_PASSIVE_TARGET_d_212_424_1r);
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st25r3916_write_reg(handle, ST25R3916_REG_MASK_RX_TIMER, 0x02);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_STOP);
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uint32_t interrupts =
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(ST25R3916_IRQ_MASK_FWL | ST25R3916_IRQ_MASK_TXE | ST25R3916_IRQ_MASK_RXS |
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ST25R3916_IRQ_MASK_RXE | ST25R3916_IRQ_MASK_PAR | ST25R3916_IRQ_MASK_CRC |
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ST25R3916_IRQ_MASK_ERR1 | ST25R3916_IRQ_MASK_ERR2 | ST25R3916_IRQ_MASK_NRE |
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ST25R3916_IRQ_MASK_EON | ST25R3916_IRQ_MASK_EOF | ST25R3916_IRQ_MASK_WU_A_X |
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ST25R3916_IRQ_MASK_WU_A);
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// Clear interrupts
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st25r3916_get_irq(handle);
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// Enable interrupts
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st25r3916_mask_irq(handle, ~interrupts);
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// Enable auto collision resolution
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st25r3916_clear_reg_bits(
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handle, ST25R3916_REG_PASSIVE_TARGET, ST25R3916_REG_PASSIVE_TARGET_d_106_ac_a);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_GOTO_SENSE);
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return furi_hal_nfc_iso14443a_common_init(handle);
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}
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static FuriHalNfcError furi_hal_nfc_iso14443a_listener_deinit(FuriHalSpiBusHandle* handle) {
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UNUSED(handle);
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if(iso14443_3a_signal) {
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iso14443_3a_signal_free(iso14443_3a_signal);
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iso14443_3a_signal = NULL;
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}
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return FuriHalNfcErrorNone;
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}
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static FuriHalNfcEvent furi_hal_nfc_iso14443_3a_listener_wait_event(uint32_t timeout_ms) {
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FuriHalNfcEvent event = furi_hal_nfc_wait_event_common(timeout_ms);
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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if(event & FuriHalNfcEventListenerActive) {
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st25r3916_set_reg_bits(
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handle, ST25R3916_REG_PASSIVE_TARGET, ST25R3916_REG_PASSIVE_TARGET_d_106_ac_a);
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}
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return event;
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}
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FuriHalNfcError furi_hal_nfc_iso14443a_poller_trx_short_frame(FuriHalNfcaShortFrame frame) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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// Disable crc check
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st25r3916_set_reg_bits(handle, ST25R3916_REG_AUX, ST25R3916_REG_AUX_no_crc_rx);
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_ISO14443A_NFC,
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(ST25R3916_REG_ISO14443A_NFC_no_tx_par | ST25R3916_REG_ISO14443A_NFC_no_rx_par),
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(ST25R3916_REG_ISO14443A_NFC_no_tx_par_off | ST25R3916_REG_ISO14443A_NFC_no_rx_par_off));
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st25r3916_write_reg(handle, ST25R3916_REG_NUM_TX_BYTES2, 0);
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uint32_t interrupts =
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(ST25R3916_IRQ_MASK_FWL | ST25R3916_IRQ_MASK_TXE | ST25R3916_IRQ_MASK_RXS |
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ST25R3916_IRQ_MASK_RXE | ST25R3916_IRQ_MASK_PAR | ST25R3916_IRQ_MASK_CRC |
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ST25R3916_IRQ_MASK_ERR1 | ST25R3916_IRQ_MASK_ERR2 | ST25R3916_IRQ_MASK_NRE);
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// Clear interrupts
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st25r3916_get_irq(handle);
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// Enable interrupts
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st25r3916_mask_irq(handle, ~interrupts);
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if(frame == FuriHalNfcaShortFrameAllReq) {
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st25r3916_direct_cmd(handle, ST25R3916_CMD_TRANSMIT_REQA);
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} else {
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st25r3916_direct_cmd(handle, ST25R3916_CMD_TRANSMIT_WUPA);
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}
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return error;
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}
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FuriHalNfcError furi_hal_nfc_iso14443a_tx_sdd_frame(const uint8_t* tx_data, size_t tx_bits) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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// No anticollision is supported in this version of library
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error = furi_hal_nfc_poller_tx(tx_data, tx_bits);
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return error;
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}
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FuriHalNfcError
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furi_hal_nfc_iso14443a_rx_sdd_frame(uint8_t* rx_data, size_t rx_data_size, size_t* rx_bits) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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UNUSED(rx_data);
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UNUSED(rx_bits);
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UNUSED(rx_data_size);
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error = furi_hal_nfc_poller_rx(rx_data, rx_data_size, rx_bits);
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// No anticollision is supported in this version of library
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return error;
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}
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FuriHalNfcError
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furi_hal_nfc_iso14443a_poller_tx_custom_parity(const uint8_t* tx_data, size_t tx_bits) {
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furi_check(tx_data);
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FuriHalNfcError err = FuriHalNfcErrorNone;
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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// Prepare tx
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st25r3916_direct_cmd(handle, ST25R3916_CMD_CLEAR_FIFO);
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st25r3916_clear_reg_bits(
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handle, ST25R3916_REG_TIMER_EMV_CONTROL, ST25R3916_REG_TIMER_EMV_CONTROL_nrt_emv);
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_ISO14443A_NFC,
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(ST25R3916_REG_ISO14443A_NFC_no_tx_par | ST25R3916_REG_ISO14443A_NFC_no_rx_par),
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(ST25R3916_REG_ISO14443A_NFC_no_tx_par | ST25R3916_REG_ISO14443A_NFC_no_rx_par));
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uint32_t interrupts =
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(ST25R3916_IRQ_MASK_FWL | ST25R3916_IRQ_MASK_TXE | ST25R3916_IRQ_MASK_RXS |
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ST25R3916_IRQ_MASK_RXE | ST25R3916_IRQ_MASK_PAR | ST25R3916_IRQ_MASK_CRC |
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ST25R3916_IRQ_MASK_ERR1 | ST25R3916_IRQ_MASK_ERR2 | ST25R3916_IRQ_MASK_NRE);
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// Clear interrupts
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st25r3916_get_irq(handle);
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// Enable interrupts
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st25r3916_mask_irq(handle, ~interrupts);
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st25r3916_write_fifo(handle, tx_data, tx_bits);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_TRANSMIT_WITHOUT_CRC);
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return err;
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}
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FuriHalNfcError furi_hal_nfc_iso14443a_listener_set_col_res_data(
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uint8_t* uid,
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uint8_t uid_len,
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uint8_t* atqa,
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uint8_t sak) {
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furi_check(uid);
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furi_check(atqa);
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FuriHalNfcError error = FuriHalNfcErrorNone;
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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// Set 4 or 7 bytes UID
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if(uid_len == 4) {
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_AUX,
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ST25R3916_REG_AUX_nfc_id_mask,
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ST25R3916_REG_AUX_nfc_id_4bytes);
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} else {
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st25r3916_change_reg_bits(
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handle,
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ST25R3916_REG_AUX,
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ST25R3916_REG_AUX_nfc_id_mask,
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ST25R3916_REG_AUX_nfc_id_7bytes);
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}
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// Write PT Memory
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uint8_t pt_memory[15] = {};
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memcpy(pt_memory, uid, uid_len);
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pt_memory[10] = atqa[0];
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pt_memory[11] = atqa[1];
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if(uid_len == 4) {
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pt_memory[12] = sak & ~0x04;
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} else {
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pt_memory[12] = 0x04;
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}
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pt_memory[13] = sak & ~0x04;
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pt_memory[14] = sak & ~0x04;
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st25r3916_write_pta_mem(handle, pt_memory, sizeof(pt_memory));
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return error;
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}
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FuriHalNfcError furi_hal_nfc_iso4443a_listener_tx(
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FuriHalSpiBusHandle* handle,
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const uint8_t* tx_data,
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size_t tx_bits) {
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FuriHalNfcError error = FuriHalNfcErrorNone;
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do {
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error = furi_hal_nfc_common_fifo_tx(handle, tx_data, tx_bits);
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if(error != FuriHalNfcErrorNone) break;
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bool tx_end = furi_hal_nfc_event_wait_for_specific_irq(handle, ST25R3916_IRQ_MASK_TXE, 10);
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if(!tx_end) {
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error = FuriHalNfcErrorCommunicationTimeout;
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break;
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}
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} while(false);
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return error;
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}
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FuriHalNfcError furi_hal_nfc_iso14443a_listener_tx_custom_parity(
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const uint8_t* tx_data,
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const uint8_t* tx_parity,
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size_t tx_bits) {
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furi_check(tx_data);
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furi_check(tx_parity);
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furi_check(iso14443_3a_signal);
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FuriHalSpiBusHandle* handle = &furi_hal_spi_bus_handle_nfc;
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st25r3916_direct_cmd(handle, ST25R3916_CMD_TRANSPARENT_MODE);
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// Reconfigure gpio for Transparent mode
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furi_hal_spi_bus_handle_deinit(&furi_hal_spi_bus_handle_nfc);
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// Send signal
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iso14443_3a_signal_tx(iso14443_3a_signal, tx_data, tx_parity, tx_bits);
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// Exit transparent mode
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furi_hal_gpio_write(&gpio_spi_r_mosi, false);
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// Configure gpio back to SPI and exit transparent
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furi_hal_spi_bus_handle_init(&furi_hal_spi_bus_handle_nfc);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_UNMASK_RECEIVE_DATA);
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return FuriHalNfcErrorNone;
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}
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FuriHalNfcError furi_hal_nfc_iso14443_3a_listener_sleep(FuriHalSpiBusHandle* handle) {
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// Enable auto collision resolution
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st25r3916_clear_reg_bits(
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handle, ST25R3916_REG_PASSIVE_TARGET, ST25R3916_REG_PASSIVE_TARGET_d_106_ac_a);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_STOP);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_GOTO_SLEEP);
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return FuriHalNfcErrorNone;
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}
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FuriHalNfcError furi_hal_nfc_iso14443_3a_listener_idle(FuriHalSpiBusHandle* handle) {
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// Enable auto collision resolution
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st25r3916_clear_reg_bits(
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handle, ST25R3916_REG_PASSIVE_TARGET, ST25R3916_REG_PASSIVE_TARGET_d_106_ac_a);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_STOP);
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st25r3916_direct_cmd(handle, ST25R3916_CMD_GOTO_SENSE);
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return FuriHalNfcErrorNone;
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}
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const FuriHalNfcTechBase furi_hal_nfc_iso14443a = {
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.poller =
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{
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.compensation =
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{
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.fdt = FURI_HAL_NFC_POLLER_FDT_COMP_FC,
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.fwt = FURI_HAL_NFC_POLLER_FWT_COMP_FC,
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},
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.init = furi_hal_nfc_iso14443a_poller_init,
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.deinit = furi_hal_nfc_iso14443a_poller_deinit,
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.wait_event = furi_hal_nfc_wait_event_common,
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.tx = furi_hal_nfc_poller_tx_common,
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.rx = furi_hal_nfc_common_fifo_rx,
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},
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.listener =
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{
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.compensation =
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{
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.fdt = FURI_HAL_NFC_ISO14443A_LISTENER_FDT_COMP_FC,
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},
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.init = furi_hal_nfc_iso14443a_listener_init,
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.deinit = furi_hal_nfc_iso14443a_listener_deinit,
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.wait_event = furi_hal_nfc_iso14443_3a_listener_wait_event,
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.tx = furi_hal_nfc_iso4443a_listener_tx,
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.rx = furi_hal_nfc_common_fifo_rx,
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.sleep = furi_hal_nfc_iso14443_3a_listener_sleep,
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.idle = furi_hal_nfc_iso14443_3a_listener_idle,
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},
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};
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