mirror of
https://github.com/DarkFlippers/unleashed-firmware.git
synced 2024-11-23 10:01:58 +03:00
338fc3afea
* Updated stack to 1.17.0 * hal: ble: Fixed stack config * Bumped stack version in config * scripts: added validation of copro stack version in update bundles * Copro: update to 1.17.2 * FuriHal: adjust tick frequency for HSE as sys clk * FuriHal: adjust systick reload on sys clock change * Sync api and format sources * scripts: updated ob.data for newer stack * FuriHal: return core2 hse pll transition on deep sleep * FuriHal: cleanup ble glue * FuriHal: rework ble glue, allow shci_send in critical section * FuriHal: sync api symbols * FuriHal: cleanup BLE glue, remove unused garbage and duplicate declarations * FuriHal: BLE glue cleanup, 2nd iteration * FuriHal: hide tick drift reports under FURI_HAL_OS_DEBUG * Lib: sync stm32wb_copro with latest dev * FuriHal: ble-glue, slightly less editable device name and duplicate definition cleanup * FuriHal: update ble config options, enable some optimizations and ext adv * FuriHal: update clock switch method documentation * FuriHal: better SNBRSA bug workaround fix * FuriHal: complete comment about tick skew * FuriHal: proper condition in clock hsi2hse transition * FuriHal: move PLL start to hse2pll routine, fix lockup caused by core2 switching to HSE before us * FuriHal: explicit HSE start before switch * FuriHal: fix documentation and move flash latency change to later stage, remove duplicate LL_RCC_SetRFWKPClockSource call --------- Co-authored-by: hedger <hedger@nanode.su> Co-authored-by: hedger <hedger@users.noreply.github.com>
35 lines
509 B
Plaintext
35 lines
509 B
Plaintext
RDP:0xAA:r
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BOR_LEV:0x4:rw
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nBOOT0:0x1:rw
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nBOOT1:0x1:rw
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nSWBOOT0:0x1:rw
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SRAM2RST:0x0:rw
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SRAM2PE:0x1:rw
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nRST_STOP:0x1:rw
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nRST_STDBY:0x1:rw
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nRSTSHDW:0x1:rw
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WWDGSW:0x1:rw
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IWGDSTDBY:0x1:rw
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IWDGSTOP:0x1:rw
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IWDGSW:0x1:rw
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IPCCDBA:0x0:rw
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ESE:0x1:r
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SFSA:0xD7:r
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FSD:0x0:r
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DDS:0x1:r
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C2OPT:0x1:r
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NBRSD:0x0:r
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SNBRSA:0xB:r
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BRSD:0x0:r
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SBRSA:0x12:r
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SBRV:0x35C00:r
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PCROP1A_STRT:0x1FF:r
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PCROP1A_END:0x0:r
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PCROP_RDP:0x1:rw
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PCROP1B_STRT:0x1FF:r
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PCROP1B_END:0x0:r
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WRP1A_STRT:0xFF:r
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WRP1A_END:0x0:r
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WRP1B_STRT:0xFF:r
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WRP1B_END:0x0:r
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