mirror of
https://github.com/DarkFlippers/unleashed-firmware.git
synced 2024-12-14 16:24:18 +03:00
e02040107b
* WIP on stripping fw * Compact FW build - use RAM_EXEC=1 COMPACT=1 DEBUG=0 * Fixed uninitialized storage struct; small fixes to compact fw * Flasher srv w/mocked flash ops * Fixed typos & accomodated FFF changes * Alternative fw startup branch * Working load & jmp to RAM fw * +manifest processing for stage loader; + crc verification for stage payload * Fixed questionable code & potential leaks * Lowered screen update rate; added radio stack update stubs; working dfu write * Console EP with manifest & stage validation * Added microtar lib; minor ui fixes for updater * Removed microtar * Removed mtar #2 * Added a better version of microtar * TAR archive api; LFS backup & restore core * Recursive backup/restore * LFS worker thread * Added system apps to loader - not visible in UI; full update process with restarts * Typo fix * Dropped BL & f6; tooling for updater WIP * Minor py fixes * Minor fixes to make it build after merge * Ported flash workaround from BL + fixed visuals * Minor cleanup * Chmod + loader app search fix * Python linter fix * Removed usb stuff & float read support for staged loader == -10% of binary size * Added backup/restore & update pb requests * Added stub impl to RPC for backup/restore/update commands * Reworked TAR to use borrowed Storage api; slightly reduced build size by removing `static string`; hidden update-related RPC behind defines * Moved backup&restore to storage * Fixed new message types * Backup/restore/update RPC impl * Moved furi_hal_crc to LL; minor fixes * CRC HAL rework to LL * Purging STM HAL * Brought back minimal DFU boot mode (no gui); additional crc state checks * Added splash screen, BROKEN usb function * Clock init rework WIP * Stripped graphics from DFU mode * Temp fix for unused static fun * WIP update picker - broken! * Fixed UI * Bumping version * Fixed RTC setup * Backup to update folder instead of ext root * Removed unused scenes & more usb remnants from staged loader * CI updates * Fixed update bundle name * Temporary restored USB handler * Attempt to prevent .text corruption * Comments on how I spent this Saturday * Added update file icon * Documentation updates * Moved common code to lib folder * Storage: more unit tests * Storage: blocking dir open, differentiate file and dir when freed. * Major refactoring; added input processing to updater to allow retrying on failures (not very useful prob). Added API for extraction of thread return value * Removed re-init check for manifest * Changed low-level path manipulation to toolbox/path.h; makefile cleanup; tiny fix in lint.py * Increased update worker stack size * Text fixes in backup CLI * Displaying number of update stages to run; removed timeout in handling errors * Bumping version * Added thread cleanup for spawner thread * Updated build targets to exclude firmware bundle from 'ALL' * Fixed makefile for update_package; skipping VCP init for update mode (ugly) * Switched github build from ALL to update_package * Added +x for dist_update.sh * Cli: add total heap size to "free" command * Moved (RAM) suffix to build version instead of git commit no. * DFU comment * Some fixes suggested by clang-tidy * Fixed recursive PREFIX macro * Makefile: gather all new rules in updater namespace. FuriHal: rename bootloader to boot, isr safe delays * Github: correct build target name in firmware build * FuriHal: move target switch to boot * Makefile: fix firmware flash * Furi, FuriHal: move kernel start to furi, early init * Drop bootloader related stuff * Drop cube. Drop bootloader linker script. * Renamed update_hl, moved constants to #defines * Moved update-related boot mode to separate bitfield * Reworked updater cli to single entry point; fixed crash on tar cleanup * Added Python replacement for dist shell scripts * Linter fixes for dist.py +x * Fixes for environment suffix * Dropped bash scripts * Added dirty build flag to version structure & interfaces * Version string escapes * Fixed flag logic in dist.py; added support for App instances being imported and not terminating the whole program * Fixed fw address in ReadMe.md * Rpc: fix crash on double screen start * Return back original boot behavior and fix jump to system bootloader * Cleanup code, add error sequence for RTC * Update firmware readme * FuriHal: drop boot, restructure RTC registers usage and add header register check * Furi goes first * Toolchain: add ccache support * Renamed update bundle dir Co-authored-by: DrZlo13 <who.just.the.doctor@gmail.com> Co-authored-by: あく <alleteam@gmail.com>
220 lines
7.7 KiB
C
220 lines
7.7 KiB
C
#include <furi_hal_clock.h>
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#include <furi.h>
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#include <stm32wbxx_ll_pwr.h>
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#include <stm32wbxx_ll_rcc.h>
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#include <stm32wbxx_ll_utils.h>
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#include <stm32wbxx_ll_cortex.h>
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#include <stm32wbxx_ll_bus.h>
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#define TAG "FuriHalClock"
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#define TICK_INT_PRIORITY 0U
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#define HS_CLOCK_IS_READY() (LL_RCC_HSE_IsReady() && LL_RCC_HSI_IsReady())
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#define LS_CLOCK_IS_READY() (LL_RCC_LSE_IsReady() && LL_RCC_LSI1_IsReady())
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void furi_hal_clock_init_early() {
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LL_Init1msTick(4000000);
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LL_SetSystemCoreClock(4000000);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3);
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}
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void furi_hal_clock_deinit_early() {
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1);
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3);
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LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1);
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
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LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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}
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void furi_hal_clock_init() {
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/* Prepare Flash memory for 64mHz system clock */
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_3);
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while(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_3)
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;
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/* HSE and HSI configuration and activation */
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LL_RCC_HSE_SetCapacitorTuning(0x26);
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LL_RCC_HSE_Enable();
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LL_RCC_HSI_Enable();
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while(!HS_CLOCK_IS_READY())
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;
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LL_RCC_HSE_EnableCSS();
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/* LSE and LSI1 configuration and activation */
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LL_PWR_EnableBkUpAccess();
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LL_RCC_LSE_SetDriveCapability(LL_RCC_LSEDRIVE_HIGH);
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LL_RCC_LSE_Enable();
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LL_RCC_LSI1_Enable();
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while(!LS_CLOCK_IS_READY())
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;
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LL_EXTI_EnableIT_0_31(
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LL_EXTI_LINE_18); /* Why? Because that's why. See RM0434, Table 61. CPU1 vector table. */
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LL_EXTI_EnableRisingTrig_0_31(LL_EXTI_LINE_18);
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LL_RCC_EnableIT_LSECSS();
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LL_RCC_LSE_EnableCSS();
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/* Main PLL configuration and activation */
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LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 8, LL_RCC_PLLR_DIV_2);
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LL_RCC_PLL_Enable();
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LL_RCC_PLL_EnableDomain_SYS();
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while(LL_RCC_PLL_IsReady() != 1)
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;
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LL_RCC_PLLSAI1_ConfigDomain_48M(
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LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1Q_DIV_2);
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LL_RCC_PLLSAI1_ConfigDomain_ADC(
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LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_2, 6, LL_RCC_PLLSAI1R_DIV_2);
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LL_RCC_PLLSAI1_Enable();
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LL_RCC_PLLSAI1_EnableDomain_48M();
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LL_RCC_PLLSAI1_EnableDomain_ADC();
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while(LL_RCC_PLLSAI1_IsReady() != 1)
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;
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/* Sysclk activation on the main PLL */
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/* Set CPU1 prescaler*/
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LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
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/* Set CPU2 prescaler*/
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LL_C2_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
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;
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/* Set AHB SHARED prescaler*/
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LL_RCC_SetAHB4Prescaler(LL_RCC_SYSCLK_DIV_1);
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/* Set APB1 prescaler*/
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LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
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/* Set APB2 prescaler*/
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LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
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/* Disable MSI */
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LL_RCC_MSI_Disable();
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while(LL_RCC_MSI_IsReady() != 0)
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;
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/* Update CMSIS variable (which can be updated also through SystemCoreClockUpdate function) */
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LL_SetSystemCoreClock(64000000);
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/* Update the time base */
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LL_InitTick(64000000, 1000);
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LL_SYSTICK_EnableIT();
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NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY);
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NVIC_EnableIRQ(SysTick_IRQn);
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LL_RCC_SetUSARTClockSource(LL_RCC_USART1_CLKSOURCE_PCLK2);
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LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1);
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LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSOURCE_PLLSAI1);
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LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
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LL_RCC_SetRNGClockSource(LL_RCC_RNG_CLKSOURCE_CLK48);
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LL_RCC_SetUSBClockSource(LL_RCC_USB_CLKSOURCE_PLLSAI1);
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LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_PLLSAI1);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
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LL_RCC_SetSMPSPrescaler(LL_RCC_SMPS_DIV_1);
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LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
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// AHB1 GRP1
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1);
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LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC);
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// LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_TSC);
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// AHB2 GRP1
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOD);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC);
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LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1);
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// AHB3 GRP1
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// LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_QUADSPI);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES2);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH);
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// APB1 GRP1
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
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// LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LCD);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB);
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// LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USB);
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
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// APB1 GRP2
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1);
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2);
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// APB2
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// LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17);
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// LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1);
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FURI_LOG_I(TAG, "Init OK");
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}
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void furi_hal_clock_switch_to_hsi() {
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LL_RCC_HSI_Enable();
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while(!LL_RCC_HSI_IsReady())
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;
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSI);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
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;
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}
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void furi_hal_clock_switch_to_pll() {
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LL_RCC_HSE_Enable();
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LL_RCC_PLL_Enable();
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while(!LL_RCC_HSE_IsReady())
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;
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while(!LL_RCC_PLL_IsReady())
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;
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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LL_RCC_SetSMPSClockSource(LL_RCC_SMPS_CLKSOURCE_HSE);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
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;
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}
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