mirror of
https://github.com/DarkFlippers/unleashed-firmware.git
synced 2024-12-15 00:33:05 +03:00
300 lines
8.5 KiB
C
300 lines
8.5 KiB
C
#include <furi-hal-flash.h>
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#include <furi-hal-bt.h>
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#include <furi.h>
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#include <ble.h>
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#include <shci.h>
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#include <stm32wbxx.h>
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#define FURI_HAL_TAG "FuriHalFlash"
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#define FURI_HAL_CRITICAL_MSG "Critical flash operation fail"
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#define FURI_HAL_FLASH_READ_BLOCK 8
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#define FURI_HAL_FLASH_WRITE_BLOCK 8
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#define FURI_HAL_FLASH_PAGE_SIZE 4096
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#define FURI_HAL_FLASH_CYCLES_COUNT 10000
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/* Free flash space borders, exported by linker */
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extern const void __free_flash_start__;
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size_t furi_hal_flash_get_base() {
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return FLASH_BASE;
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}
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size_t furi_hal_flash_get_read_block_size() {
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return FURI_HAL_FLASH_READ_BLOCK;
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}
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size_t furi_hal_flash_get_write_block_size() {
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return FURI_HAL_FLASH_WRITE_BLOCK;
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}
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size_t furi_hal_flash_get_page_size() {
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return FURI_HAL_FLASH_PAGE_SIZE;
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}
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size_t furi_hal_flash_get_cycles_count() {
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return FURI_HAL_FLASH_CYCLES_COUNT;
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}
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const void* furi_hal_flash_get_free_start_address() {
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return &__free_flash_start__;
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}
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const void* furi_hal_flash_get_free_end_address() {
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uint32_t sfr_reg_val = READ_REG(FLASH->SFR);
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uint32_t sfsa = (READ_BIT(sfr_reg_val, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos);
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return (const void *)((sfsa * FLASH_PAGE_SIZE) + FLASH_BASE);
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}
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size_t furi_hal_flash_get_free_page_start_address() {
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size_t start = (size_t)furi_hal_flash_get_free_start_address();
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size_t page_start = start - start % FURI_HAL_FLASH_PAGE_SIZE;
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if (page_start != start) {
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page_start += FURI_HAL_FLASH_PAGE_SIZE;
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}
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return page_start;
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}
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size_t furi_hal_flash_get_free_page_count() {
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size_t end = (size_t)furi_hal_flash_get_free_end_address();
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size_t page_start = (size_t)furi_hal_flash_get_free_page_start_address();
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return (end-page_start) / FURI_HAL_FLASH_PAGE_SIZE;
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}
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static void furi_hal_flash_unlock() {
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/* verify Flash is locked */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U);
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/* Authorize the FLASH Registers access */
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WRITE_REG(FLASH->KEYR, FLASH_KEY1);
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WRITE_REG(FLASH->KEYR, FLASH_KEY2);
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/* verify Flash is unlock */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U);
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}
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static void furi_hal_flash_lock(void) {
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/* verify Flash is unlocked */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U);
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/* Set the LOCK Bit to lock the FLASH Registers access */
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/* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
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SET_BIT(FLASH->CR, FLASH_CR_LOCK);
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/* verify Flash is locked */
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furi_check(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U);
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}
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static void furi_hal_flash_begin_with_core2(bool erase_flag) {
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// Take flash controller ownership
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while (HAL_HSEM_FastTake(CFG_HW_FLASH_SEMID) != HAL_OK) {
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taskYIELD();
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}
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// Unlock flash operation
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furi_hal_flash_unlock();
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// Erase activity notification
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if(erase_flag) SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_ON);
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while(true) {
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// Wait till flash controller become usable
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while(LL_FLASH_IsActiveFlag_OperationSuspended()) {
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taskYIELD();
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};
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// Just a little more love
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taskENTER_CRITICAL();
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// Actually we already have mutex for it, but specification is specification
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if (HAL_HSEM_IsSemTaken(CFG_HW_BLOCK_FLASH_REQ_BY_CPU1_SEMID)) {
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taskEXIT_CRITICAL();
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continue;
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}
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// Take sempahopre and prevent core2 from anyting funky
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if (HAL_HSEM_FastTake(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID) != HAL_OK) {
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taskEXIT_CRITICAL();
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continue;
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}
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break;
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}
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}
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static void furi_hal_flash_begin(bool erase_flag) {
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// Acquire dangerous ops mutex
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furi_hal_bt_lock_core2();
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// If Core2 is running use IPC locking
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if(furi_hal_bt_is_alive()) {
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furi_hal_flash_begin_with_core2(erase_flag);
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} else {
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furi_hal_flash_unlock();
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}
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}
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static void furi_hal_flash_end_with_core2(bool erase_flag) {
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// Funky ops are ok at this point
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HAL_HSEM_Release(CFG_HW_BLOCK_FLASH_REQ_BY_CPU2_SEMID, 0);
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// Task switching is ok
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taskEXIT_CRITICAL();
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// Doesn't make much sense, does it?
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while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
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taskYIELD();
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}
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// Erase activity over, core2 can continue
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if(erase_flag) SHCI_C2_FLASH_EraseActivity(ERASE_ACTIVITY_OFF);
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// Lock flash controller
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furi_hal_flash_lock();
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// Release flash controller ownership
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HAL_HSEM_Release(CFG_HW_FLASH_SEMID, 0);
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}
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static void furi_hal_flash_end(bool erase_flag) {
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// If Core2 is running use IPC locking
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if(furi_hal_bt_is_alive()) {
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furi_hal_flash_end_with_core2(erase_flag);
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} else {
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furi_hal_flash_lock();
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}
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// Release dangerous ops mutex
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furi_hal_bt_unlock_core2();
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}
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static void furi_hal_flush_cache(void) {
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/* Flush instruction cache */
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if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) == FLASH_ACR_ICEN) {
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/* Disable instruction cache */
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__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
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/* Reset instruction cache */
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__HAL_FLASH_INSTRUCTION_CACHE_RESET();
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/* Enable instruction cache */
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__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
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}
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/* Flush data cache */
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if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) == FLASH_ACR_DCEN) {
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/* Disable data cache */
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__HAL_FLASH_DATA_CACHE_DISABLE();
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/* Reset data cache */
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__HAL_FLASH_DATA_CACHE_RESET();
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/* Enable data cache */
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__HAL_FLASH_DATA_CACHE_ENABLE();
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}
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}
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HAL_StatusTypeDef furi_hal_flash_wait_last_operation(uint32_t timeout) {
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uint32_t error = 0;
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uint32_t countdown = 0;
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// Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
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// Even if the FLASH operation fails, the BUSY flag will be reset and an error
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// flag will be set
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countdown = timeout;
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while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) {
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if(LL_SYSTICK_IsActiveCounterFlag()) {
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countdown--;
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}
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if (countdown == 0) {
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return HAL_TIMEOUT;
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}
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}
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/* Check FLASH operation error flags */
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error = FLASH->SR;
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/* Check FLASH End of Operation flag */
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if ((error & FLASH_FLAG_EOP) != 0U) {
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/* Clear FLASH End of Operation pending bit */
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__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
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}
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/* Now update error variable to only error value */
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error &= FLASH_FLAG_SR_ERRORS;
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furi_check(error == 0);
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/* clear error flags */
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__HAL_FLASH_CLEAR_FLAG(error);
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/* Wait for control register to be written */
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countdown = timeout;
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while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY)) {
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if(LL_SYSTICK_IsActiveCounterFlag()) {
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countdown--;
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}
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if (countdown == 0) {
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return HAL_TIMEOUT;
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}
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}
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return HAL_OK;
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}
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bool furi_hal_flash_erase(uint8_t page) {
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furi_hal_flash_begin(true);
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// Ensure that controller state is valid
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furi_check(FLASH->SR == 0);
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/* Verify that next operation can be proceed */
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furi_check(furi_hal_flash_wait_last_operation(FLASH_TIMEOUT_VALUE) == HAL_OK);
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/* Select page and start operation */
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MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT));
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/* Wait for last operation to be completed */
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furi_check(furi_hal_flash_wait_last_operation(FLASH_TIMEOUT_VALUE) == HAL_OK);
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/* If operation is completed or interrupted, disable the Page Erase Bit */
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CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
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/* Flush the caches to be sure of the data consistency */
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furi_hal_flush_cache();
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furi_hal_flash_end(true);
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return true;
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}
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bool furi_hal_flash_write_dword(size_t address, uint64_t data) {
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furi_hal_flash_begin(false);
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// Ensure that controller state is valid
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furi_check(FLASH->SR == 0);
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/* Check the parameters */
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furi_check(IS_ADDR_ALIGNED_64BITS(address));
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furi_check(IS_FLASH_PROGRAM_ADDRESS(address));
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/* Set PG bit */
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SET_BIT(FLASH->CR, FLASH_CR_PG);
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/* Program first word */
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*(uint32_t *)address = (uint32_t)data;
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// Barrier to ensure programming is performed in 2 steps, in right order
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// (independently of compiler optimization behavior)
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__ISB();
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/* Program second word */
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*(uint32_t *)(address + 4U) = (uint32_t)(data >> 32U);
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/* Wait for last operation to be completed */
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furi_check(furi_hal_flash_wait_last_operation(FLASH_TIMEOUT_VALUE) == HAL_OK);
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/* If the program operation is completed, disable the PG or FSTPG Bit */
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CLEAR_BIT(FLASH->CR, FLASH_CR_PG);
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furi_hal_flash_end(false);
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return true;
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}
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