mirror of
https://github.com/DarkFlippers/unleashed-firmware.git
synced 2024-12-21 04:11:48 +03:00
d92b0a82cc
"A long time ago in a galaxy far, far away...." we started NFC subsystem refactoring. Starring: - @gornekich - NFC refactoring project lead, architect, senior developer - @gsurkov - architect, senior developer - @RebornedBrain - senior developer Supporting roles: - @skotopes, @DrZlo13, @hedger - general architecture advisors, code review - @Astrrra, @doomwastaken, @Hellitron, @ImagineVagon333 - quality assurance Special thanks: @bettse, @pcunning, @nxv, @noproto, @AloneLiberty and everyone else who has been helping us all this time and contributing valuable knowledges, ideas and source code.
258 lines
8.2 KiB
C
258 lines
8.2 KiB
C
#include "st25r3916_reg.h"
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#include <furi.h>
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#define ST25R3916_WRITE_MODE \
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(0U << 6) /*!< ST25R3916 Operation Mode: Write */
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#define ST25R3916_READ_MODE \
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(1U << 6) /*!< ST25R3916 Operation Mode: Read */
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#define ST25R3916_CMD_MODE \
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(3U << 6) /*!< ST25R3916 Operation Mode: Direct Command */
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#define ST25R3916_FIFO_LOAD \
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(0x80U) /*!< ST25R3916 Operation Mode: FIFO Load */
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#define ST25R3916_FIFO_READ \
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(0x9FU) /*!< ST25R3916 Operation Mode: FIFO Read */
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#define ST25R3916_PT_A_CONFIG_LOAD \
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(0xA0U) /*!< ST25R3916 Operation Mode: Passive Target Memory A-Config Load */
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#define ST25R3916_PT_F_CONFIG_LOAD \
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(0xA8U) /*!< ST25R3916 Operation Mode: Passive Target Memory F-Config Load */
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#define ST25R3916_PT_TSN_DATA_LOAD \
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(0xACU) /*!< ST25R3916 Operation Mode: Passive Target Memory TSN Load */
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#define ST25R3916_PT_MEM_READ \
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(0xBFU) /*!< ST25R3916 Operation Mode: Passive Target Memory Read */
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#define ST25R3916_CMD_LEN \
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(1U) /*!< ST25R3916 CMD length */
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#define ST25R3916_FIFO_DEPTH (512U)
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#define ST25R3916_BUF_LEN \
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(ST25R3916_CMD_LEN + \
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ST25R3916_FIFO_DEPTH) /*!< ST25R3916 communication buffer: CMD + FIFO length */
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static void st25r3916_reg_tx_byte(FuriHalSpiBusHandle* handle, uint8_t byte) {
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uint8_t val = byte;
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furi_hal_spi_bus_tx(handle, &val, 1, 5);
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}
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void st25r3916_read_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* val) {
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furi_assert(handle);
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st25r3916_read_burst_regs(handle, reg, val, 1);
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}
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void st25r3916_read_burst_regs(
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FuriHalSpiBusHandle* handle,
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uint8_t reg_start,
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uint8_t* values,
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uint8_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_assert(length);
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furi_hal_gpio_write(handle->cs, false);
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if(reg_start & ST25R3916_SPACE_B) {
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// Send direct command first
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st25r3916_reg_tx_byte(handle, ST25R3916_CMD_SPACE_B_ACCESS);
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}
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st25r3916_reg_tx_byte(handle, (reg_start & ~ST25R3916_SPACE_B) | ST25R3916_READ_MODE);
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furi_hal_spi_bus_rx(handle, values, length, 5);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_write_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t val) {
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furi_assert(handle);
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uint8_t reg_val = val;
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st25r3916_write_burst_regs(handle, reg, ®_val, 1);
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}
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void st25r3916_write_burst_regs(
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FuriHalSpiBusHandle* handle,
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uint8_t reg_start,
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const uint8_t* values,
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uint8_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_assert(length);
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furi_hal_gpio_write(handle->cs, false);
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if(reg_start & ST25R3916_SPACE_B) {
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// Send direct command first
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st25r3916_reg_tx_byte(handle, ST25R3916_CMD_SPACE_B_ACCESS);
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}
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st25r3916_reg_tx_byte(handle, (reg_start & ~ST25R3916_SPACE_B) | ST25R3916_WRITE_MODE);
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furi_hal_spi_bus_tx(handle, values, length, 5);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_reg_write_fifo(FuriHalSpiBusHandle* handle, const uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_assert(length);
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furi_assert(length <= ST25R3916_FIFO_DEPTH);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_FIFO_LOAD);
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furi_hal_spi_bus_tx(handle, buff, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_reg_read_fifo(FuriHalSpiBusHandle* handle, uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_assert(length);
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furi_assert(length <= ST25R3916_FIFO_DEPTH);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_FIFO_READ);
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furi_hal_spi_bus_rx(handle, buff, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_write_pta_mem(FuriHalSpiBusHandle* handle, const uint8_t* values, size_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_assert(length);
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furi_assert(length <= ST25R3916_PTM_LEN);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_A_CONFIG_LOAD);
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furi_hal_spi_bus_tx(handle, values, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_read_pta_mem(FuriHalSpiBusHandle* handle, uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_assert(length);
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furi_assert(length <= ST25R3916_PTM_LEN);
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uint8_t tmp_buff[ST25R3916_PTM_LEN + 1];
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_MEM_READ);
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furi_hal_spi_bus_rx(handle, tmp_buff, length + 1, 200);
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furi_hal_gpio_write(handle->cs, true);
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memcpy(buff, tmp_buff + 1, length);
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}
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void st25r3916_write_ptf_mem(FuriHalSpiBusHandle* handle, const uint8_t* values, size_t length) {
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furi_assert(handle);
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furi_assert(values);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_F_CONFIG_LOAD);
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furi_hal_spi_bus_tx(handle, values, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_write_pttsn_mem(FuriHalSpiBusHandle* handle, uint8_t* buff, size_t length) {
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furi_assert(handle);
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furi_assert(buff);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_PT_TSN_DATA_LOAD);
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furi_hal_spi_bus_tx(handle, buff, length, 200);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_direct_cmd(FuriHalSpiBusHandle* handle, uint8_t cmd) {
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furi_assert(handle);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, cmd | ST25R3916_CMD_MODE);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_read_test_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t* val) {
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furi_assert(handle);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_CMD_TEST_ACCESS);
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st25r3916_reg_tx_byte(handle, reg | ST25R3916_READ_MODE);
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furi_hal_spi_bus_rx(handle, val, 1, 5);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_write_test_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t val) {
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furi_assert(handle);
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furi_hal_gpio_write(handle->cs, false);
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st25r3916_reg_tx_byte(handle, ST25R3916_CMD_TEST_ACCESS);
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st25r3916_reg_tx_byte(handle, reg | ST25R3916_WRITE_MODE);
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furi_hal_spi_bus_tx(handle, &val, 1, 5);
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furi_hal_gpio_write(handle->cs, true);
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}
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void st25r3916_clear_reg_bits(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t clr_mask) {
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furi_assert(handle);
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uint8_t reg_val = 0;
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st25r3916_read_reg(handle, reg, ®_val);
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if((reg_val & ~clr_mask) != reg_val) {
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reg_val &= ~clr_mask;
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st25r3916_write_reg(handle, reg, reg_val);
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}
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}
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void st25r3916_set_reg_bits(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t set_mask) {
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furi_assert(handle);
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uint8_t reg_val = 0;
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st25r3916_read_reg(handle, reg, ®_val);
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if((reg_val | set_mask) != reg_val) {
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reg_val |= set_mask;
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st25r3916_write_reg(handle, reg, reg_val);
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}
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}
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void st25r3916_change_reg_bits(
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FuriHalSpiBusHandle* handle,
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uint8_t reg,
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uint8_t mask,
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uint8_t value) {
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furi_assert(handle);
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st25r3916_modify_reg(handle, reg, mask, (mask & value));
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}
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void st25r3916_modify_reg(
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FuriHalSpiBusHandle* handle,
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uint8_t reg,
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uint8_t clr_mask,
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uint8_t set_mask) {
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furi_assert(handle);
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uint8_t reg_val = 0;
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uint8_t new_val = 0;
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st25r3916_read_reg(handle, reg, ®_val);
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new_val = (reg_val & ~clr_mask) | set_mask;
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if(new_val != reg_val) {
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st25r3916_write_reg(handle, reg, new_val);
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}
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}
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void st25r3916_change_test_reg_bits(
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FuriHalSpiBusHandle* handle,
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uint8_t reg,
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uint8_t mask,
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uint8_t value) {
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furi_assert(handle);
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uint8_t reg_val = 0;
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uint8_t new_val = 0;
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st25r3916_read_test_reg(handle, reg, ®_val);
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new_val = (reg_val & ~mask) | (mask & value);
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if(new_val != reg_val) {
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st25r3916_write_test_reg(handle, reg, new_val);
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}
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}
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bool st25r3916_check_reg(FuriHalSpiBusHandle* handle, uint8_t reg, uint8_t mask, uint8_t val) {
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furi_assert(handle);
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uint8_t reg_val = 0;
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st25r3916_read_reg(handle, reg, ®_val);
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return ((reg_val & mask) == val);
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}
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