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[arm] Update for Word32 Thumb GPR initialization and register count.

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Kevin Quick 2018-08-10 15:41:22 -07:00
parent 5597b12c01
commit 031a03a7c9
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2 changed files with 8 additions and 8 deletions
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4
macaw-arm/src/Data/Macaw/ARM/ARMReg.hs
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@ -31,7 +31,7 @@ import Data.Parameterized.Some ( Some(..) )
import qualified Data.Parameterized.TH.GADT as TH
import Data.Semigroup
import qualified Data.Set as Set
import Data.Word ( Word8 )
import Data.Word ( Word32 )
import qualified Dismantle.ARM.Operands as ARMOperands
import GHC.TypeLits
import Language.Haskell.TH
@ -44,7 +44,7 @@ import qualified Text.PrettyPrint.HughesPJClass as PP
data ARMReg tp where
-- n.b. The Thumb (T32) register model is the same as the ARM
-- (A32) model, so just use the latter to define registers.
ARM_GP :: (w ~ MC.RegAddrWidth ARMReg, 1 <= w) => Word8 -> ARMReg (BVType w)
ARM_GP :: (w ~ MC.RegAddrWidth ARMReg, 1 <= w) => Word32 -> ARMReg (BVType w)
-- GPR15 is normally aliased with the PC, but not always,
-- so track it separately and use semantics definitions
-- to manage the synchronization.

12
macaw-arm/src/Data/Macaw/ARM/Operand.hs
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@ -27,11 +27,11 @@ import qualified SemMC.Architecture.AArch32 as ARM
instance ExtractValue ARM.AArch32 A32Operand.GPR (BVType 32) where
extractValue r = G.getRegValue (Reg.ARM_GP $ A32Operand.unGPR r)
extractValue r = G.getRegValue (Reg.ARM_GP $ fromIntegral $ A32Operand.unGPR r)
instance ToRegister A32Operand.GPR Reg.ARMReg (BVType 32) where
toRegister = Reg.ARM_GP . A32Operand.unGPR
toRegister = Reg.ARM_GP . fromIntegral . A32Operand.unGPR
instance ExtractValue ARM.AArch32 (Maybe A32Operand.GPR) (BVType 32) where
@ -78,11 +78,11 @@ instance ExtractValue ARM.AArch32 Word8 (BVType 8) where
-- ----------------------------------------------------------------------
instance ExtractValue ARM.AArch32 T32Operand.GPR (BVType 32) where
extractValue r = G.getRegValue (Reg.ARM_GP $ T32Operand.unGPR r)
extractValue r = G.getRegValue (Reg.ARM_GP $ fromIntegral $ T32Operand.unGPR r)
instance ToRegister T32Operand.GPR Reg.ARMReg (BVType 32) where
toRegister = Reg.ARM_GP . T32Operand.unGPR
toRegister = Reg.ARM_GP . fromIntegral . T32Operand.unGPR
instance ExtractValue ARM.AArch32 (Maybe T32Operand.GPR) (BVType 32) where
@ -104,10 +104,10 @@ instance ExtractValue ARM.AArch32 T32Operand.AddrModeIs4 (BVType 32) where
extractValue = return . MC.BVValue NR.knownNat . toInteger . T32Operand.addrModeIs4ToBits
instance ExtractValue ARM.AArch32 T32Operand.LowGPR (BVType 32) where
extractValue r = G.getRegValue (Reg.ARM_GP $ T32Operand.unLowGPR r)
extractValue r = G.getRegValue (Reg.ARM_GP $ fromIntegral $ T32Operand.unLowGPR r)
instance ToRegister T32Operand.LowGPR Reg.ARMReg (BVType 32) where
toRegister = Reg.ARM_GP . T32Operand.unLowGPR
toRegister = Reg.ARM_GP . fromIntegral . T32Operand.unLowGPR
instance ExtractValue ARM.AArch32 (Maybe T32Operand.LowGPR) (BVType 32) where
extractValue mgpr =