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Port x86-symbolic to the new pointer representation
This commit is contained in:
Iavor Diatchki
parent
ad5f7ceddb
commit
b5995421ea
@ -15,7 +15,8 @@ library
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macaw-symbolic,
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macaw-x86,
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mtl,
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parameterized-utils
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parameterized-utils,
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crucible-llvm
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hs-source-dirs: src
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exposed-modules:
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@ -9,6 +9,7 @@
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{-# Language EmptyCase #-}
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{-# Language MultiWayIf #-}
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{-# Language PatternGuards #-}
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{-# Language PatternSynonyms #-}
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{-# Language RecordWildCards #-}
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{-# Language FlexibleContexts #-}
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module Data.Macaw.X86.Crucible
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@ -47,6 +48,10 @@ import Lang.Crucible.Solver.Symbol(userSymbol)
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import Lang.Crucible.Types
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import qualified Lang.Crucible.Vector as V
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import Lang.Crucible.Utils.Endian(Endian(..))
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import Lang.Crucible.LLVM.MemModel (LLVMPointerType)
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import Lang.Crucible.LLVM.MemModel.Pointer
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(projectLLVM_bv, pattern LLVMPointerRepr, llvmPointer_bv)
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import qualified Data.Macaw.Types as M
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import Data.Macaw.Symbolic.CrucGen(MacawExt)
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@ -78,12 +83,15 @@ data Sym s = Sym { symIface :: s
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data SymFuns s = SymFuns
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{ fnAesEnc ::
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SymFn s (EmptyCtx ::> BaseBVType 128 ::> BaseBVType 128) (BaseBVType 128)
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-- ^ One round of AES
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, fnAesEncLast ::
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SymFn s (EmptyCtx ::> BaseBVType 128 ::> BaseBVType 128) (BaseBVType 128)
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-- ^ Last round of AES
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, fnClMul ::
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SymFn s (EmptyCtx ::> BaseBVType 64 ::> BaseBVType 64) (BaseBVType 128)
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-- ^ Carryless multiplication
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}
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@ -114,12 +122,11 @@ pureSem :: (IsSymInterface sym) =>
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IO (RegValue sym (ToCrucibleType mt)) -- ^ Resulting value
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pureSem sym fn =
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case fn of
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M.EvenParity x ->
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evalE sym $
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app $ Not $
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foldr1 xor [ bvTestBit (getVal x) i | i <- [ 0 .. 7 ] ]
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where xor a b = app (BoolXor a b)
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M.EvenParity x0 ->
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do x <- getBitVal (symIface sym) x0
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evalE sym $ app $ Not $ foldr1 xor [ bvTestBit x i | i <- [ 0 .. 7 ] ]
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where xor a b = app (BoolXor a b)
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M.VOp1 w op1 x ->
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case op1 of
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@ -149,55 +156,56 @@ pureSem sym fn =
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(V.split i n16 xs)
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(V.split i n16 ys)
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M.VPCLMULQDQ i -> unpack2 LittleEndian w n64 x y $ \xs ys ->
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M.VPCLMULQDQ i -> unpack2 (symIface sym) LittleEndian w n64 x y $
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\xs ys ->
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case testEquality (V.length xs) n2 of
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Just Refl ->
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do let v1 = if i `testBit` 0 then V.elemAt n1 xs
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else V.elemAt n0 xs
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v2 = if i `testBit` 4 then V.elemAt n1 ys
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else V.elemAt n0 ys
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x1 <- evalE sym v1
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x2 <- evalE sym v2
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let f = fnClMul (symFuns sym)
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ps = extend (extend empty x2) x1
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applySymFn (symIface sym) f ps
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llvmPointer_bv (symIface sym) =<<
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applySymFn (symIface sym) f ps
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_ -> fail "Unepected size for VPCLMULQDQ"
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M.VAESEnc
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| Just Refl <- testEquality w n128 ->
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do let f = fnAesEnc (symFuns sym)
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state = toVal x
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key = toVal y
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ps = extend (extend empty state) key
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applySymFn (symIface sym) f ps
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do let f = fnAesEnc (symFuns sym)
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s = symIface sym
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state <- toValBV s x
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key <- toValBV s y
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let ps = extend (extend empty state) key
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llvmPointer_bv s =<< applySymFn s f ps
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| otherwise -> fail "Unexpecte size for AESEnc"
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M.VAESEncLast
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| Just Refl <- testEquality w n128 ->
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do let f = fnAesEncLast (symFuns sym)
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state = toVal x
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key = toVal y
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ps = extend (extend empty state) key
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applySymFn (symIface sym) f ps
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do let f = fnAesEncLast (symFuns sym)
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s = symIface sym
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state <- toValBV s x
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key <- toValBV s y
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let ps = extend (extend empty state) key
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llvmPointer_bv s =<< applySymFn s f ps
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| otherwise -> fail "Unexpecte size for AESEncLast"
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M.PointwiseShiftL elNum elSz shSz bits amt ->
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vecOp1 sym LittleEndian (natMultiply elNum elSz) elSz bits $ \xs ->
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fmap (\x -> bvShiftL elSz shSz x (getVal amt)) xs
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do amt' <- getBitVal (symIface sym) amt
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vecOp1 sym LittleEndian (natMultiply elNum elSz) elSz bits $ \xs ->
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fmap (\x -> bvShiftL elSz shSz x amt') xs
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M.Pointwise2 elNum elSz op v1 v2 ->
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vecOp2 sym LittleEndian (natMultiply elNum elSz) elSz v1 v2 $ \xs ys ->
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V.zipWith (semPointwise op elSz) xs ys
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semPointwise :: (1 <= w) =>
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M.AVXPointWiseOp2 -> NatRepr w ->
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E sym (BVType w) -> E sym (BVType w) -> E sym (BVType w)
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@ -249,7 +257,6 @@ divExact n x k = withDivModNat n x $ \i r ->
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Nothing -> error "divExact: not a multiple of 16"
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vecOp1 :: (IsSymInterface sym, 1 <= c) =>
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Sym sym {- ^ Simulator -} ->
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Endian {- ^ How to split-up the bit-vector -} ->
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@ -259,10 +266,10 @@ vecOp1 :: (IsSymInterface sym, 1 <= c) =>
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(forall n. (1 <= n, (n * c) ~ w) =>
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V.Vector n (E sym (BVType c)) -> V.Vector n (E sym (BVType c))) ->
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-- ^ Definition of operation
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IO (RegValue sym (BVType w)) -- ^ The final result.
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IO (RegValue sym (LLVMPointerType w)) -- ^ The final result.
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vecOp1 sym endian totLen elLen x f =
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unpack endian totLen elLen x $ \v ->
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evalE sym (V.toBV endian elLen (f v))
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unpack (symIface sym) endian totLen elLen x $ \v ->
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llvmPointer_bv (symIface sym) =<< evalE sym (V.toBV endian elLen (f v))
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vecOp2 :: (IsSymInterface sym, 1 <= c) =>
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@ -277,10 +284,10 @@ vecOp2 :: (IsSymInterface sym, 1 <= c) =>
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V.Vector n (E sym (BVType c)) ->
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V.Vector n (E sym (BVType c))) ->
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-- ^ Definition of operation
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IO (RegValue sym (BVType w)) -- ^ The final result.
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IO (RegValue sym (LLVMPointerType w)) -- ^ The final result.
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vecOp2 sym endian totLen elLen x y f =
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unpack2 endian totLen elLen x y $ \u v ->
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evalE sym (V.toBV endian elLen (f u v))
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unpack2 (symIface sym) endian totLen elLen x y $ \u v ->
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llvmPointer_bv (symIface sym) =<< evalE sym (V.toBV endian elLen (f u v))
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bitOp2 :: (IsSymInterface sym) =>
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@ -289,26 +296,35 @@ bitOp2 :: (IsSymInterface sym) =>
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AtomWrapper (RegEntry sym) (M.BVType w) {- ^ Input 2 -} ->
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(E sym (BVType w) -> E sym (BVType w) -> App () (E sym) (BVType w)) ->
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-- ^ The definition of the operation
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IO (RegValue sym (BVType w)) {- ^ The result -}
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bitOp2 sym x y f = evalE sym $ app $ f (getVal x) (getVal y)
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IO (RegValue sym (LLVMPointerType w)) {- ^ The result -}
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bitOp2 sym x y f =
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do let s = symIface sym
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x' <- getBitVal s x
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y' <- getBitVal s y
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llvmPointer_bv s =<< evalE sym (app (f x' y'))
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-- | Split up a bit-vector into a vector.
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-- Even though X86 is little endian for memory accesses, this function
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-- is parameterized by endianness, as some instructions are more naturally
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-- expressed by splitting big-endian-wise (e.g., shifts)
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unpack ::
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(1 <= c) =>
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(1 <= c, IsSymInterface sym) =>
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sym ->
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Endian ->
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NatRepr w {- ^ Original length -} ->
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NatRepr c {- ^ Size of each chunk -} ->
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AtomWrapper (RegEntry sym) (M.BVType w) {- ^ Input value -} ->
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(forall n. (1 <= n, (n * c) ~ w) => V.Vector n (E sym (BVType c)) -> IO a) ->
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IO a
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unpack e w c v k = divExact w c $ \n -> k (V.fromBV e n c (getVal v))
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unpack sym e w c v k = divExact w c $ \n ->
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do b <- getBitVal sym v
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k (V.fromBV e n c b)
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-- | Split up two bit-vectors into sub-chunks.
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unpack2 ::
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(1 <= c) =>
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(1 <= c, IsSymInterface sym) =>
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sym ->
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Endian ->
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NatRepr w ->
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NatRepr c ->
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@ -319,16 +335,33 @@ unpack2 ::
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V.Vector n (E sym (BVType c)) ->
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IO a) ->
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IO a
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unpack2 e w c v1 v2 k =
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divExact w c $ \n -> k (V.fromBV e n c (getVal v1))
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(V.fromBV e n c (getVal v2))
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unpack2 sym e w c v1 v2 k =
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divExact w c $ \n ->
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do v1' <- getBitVal sym v1
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v2' <- getBitVal sym v2
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k (V.fromBV e n c v1') (V.fromBV e n c v2')
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getVal :: AtomWrapper (RegEntry sym) mt -> E sym (ToCrucibleType mt)
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getVal (AtomWrapper x) = Val x
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toVal :: AtomWrapper (RegEntry sym) mt -> RegValue sym (ToCrucibleType mt)
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toVal (AtomWrapper x) = regValue x
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getBitVal ::
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IsSymInterface sym =>
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sym ->
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AtomWrapper (RegEntry sym) (M.BVType w) ->
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IO (E sym (BVType w))
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getBitVal sym (AtomWrapper x) =
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do v <- projectLLVM_bv sym (regValue x)
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case regType x of
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LLVMPointerRepr w -> return (ValBV w v)
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_ -> error "getBitVal: impossible"
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toValBV ::
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IsSymInterface sym =>
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sym ->
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AtomWrapper (RegEntry sym) (M.BVType w) ->
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IO (RegValue sym (BVType w))
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toValBV sym (AtomWrapper x) = projectLLVM_bv sym (regValue x)
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--------------------------------------------------------------------------------
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@ -339,8 +372,9 @@ toVal (AtomWrapper x) = regValue x
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evalE :: IsSymInterface sym => Sym sym -> E sym t -> IO (RegValue sym t)
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evalE sym e = case e of
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Val x -> return (regValue x)
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Expr a -> evalApp sym a
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ValBool x -> return x
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ValBV _ x -> return x
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Expr a -> evalApp sym a
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evalApp :: forall sym t. IsSymInterface sym =>
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Sym sym -> App () (E sym) t -> IO (RegValue sym t)
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@ -352,7 +386,8 @@ evalApp x = C.evalApp (symIface x) (symTys x) logger evalExt (evalE x)
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evalExt _ y = case y of {}
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data E :: * -> CrucibleType -> * where
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Val :: RegEntry sym t -> E sym t
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ValBool :: RegValue sym BoolType -> E sym BoolType
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ValBV :: (1 <= w) => NatRepr w -> RegValue sym (BVType w) -> E sym (BVType w)
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Expr :: App () (E sym) t -> E sym t
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instance IsExpr (E sym) where
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@ -363,7 +398,8 @@ instance IsExpr (E sym) where
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_ -> Nothing
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exprType e = case e of
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Expr a -> appType a
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Val r -> regType r
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ValBool _ -> knownRepr
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ValBV n _ -> BVRepr n
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bv :: (KnownNat w, 1 <= w) => Int -> E sym (BVType w)
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@ -397,6 +433,7 @@ bvShiftL w i vw vi = app (BVShl w vw amt)
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NatCaseGT LeqProof -> app (BVTrunc w i vi)
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--------------------------------------------------------------------------------
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n0 :: NatRepr 0
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