Tristan Ravitch
fabb8799d8
Make tests less chatty
2020-04-08 19:57:26 -07:00
Tristan Ravitch
958aeaa3ed
Remove the nested mux match rule from macaw core
...
We can now do enough rewriting in the ARM backend that it isn't needed. This
adds extra ARM rewriting rules and a term cache to make matching easier.
2020-04-08 19:46:32 -07:00
Tristan Ravitch
d865811701
In ARM, read the current register value from a snapshot
...
We were reading partially updated values that were committed to the register
state out-of-order, yielding some bad results.
This commit takes a snapshot of the register state before executing each
instruction and only reads register values from the snapshot.
2020-04-08 11:54:28 -07:00
Tristan Ravitch
36c67eb586
Fix an error introduced during cleanup
2020-04-08 07:27:28 -07:00
Tristan Ravitch
b0683c06a9
Poke the ARM simplifier into working
...
The generic simplifier needed a case to handle xor.
The more specific simplifier needed a case to coalesce adjacent additions.
2020-04-08 02:23:47 -07:00
Tristan Ravitch
997e435a0c
WIP Debugging rewriting rules
...
They fire sometimes and definitely clean up the IR, but they are missing a few
key cases still
2020-04-08 00:04:51 -07:00
Daniel Matichuk
2257c18d65
use appendStmt properly for SIMD write mode
2020-04-06 21:37:47 -07:00
Daniel Matichuk
464835403e
import fixup
2020-04-06 20:53:06 -07:00
Daniel Matichuk
a2ee426714
Merge remote-tracking branch 'origin/feature/asl' into feature/asl
2020-04-06 20:48:34 -07:00
Daniel Matichuk
c3bdbfd191
add guarded register/memory writes
2020-04-06 20:38:39 -07:00
Tristan Ravitch
5e5c90c993
Updates to the simplifier and call recognition
2020-04-06 17:56:22 -07:00
Tristan Ravitch
b8c3e65389
Add a test with a call
2020-04-06 15:56:43 -07:00
Tristan Ravitch
c5fe84f97c
Add a missing instance for ARMReg
2020-04-05 21:17:47 -07:00
Tristan Ravitch
1fa9b86b26
Rename macaw-asl to macaw-aarch32
...
This is more descriptive, especially since we will eventually have
macaw-aarch32 (also derived from the ASL specs)
2020-04-05 15:16:39 -07:00
