mirror of
https://github.com/GaloisInc/macaw.git
synced 2024-12-02 10:54:04 +03:00
82640e7a4b
* riscv: added grift as submodule
* added macaw-riscv project
* make arch polykinded everywhere in macaw base
* stubbed out riscv_info
* update grift
* started on RISCVReg
* started on RISCVReg
* RegisterInfo instance for RISCVReg (a few unimplemented fields)
* filled out archRegSet
* filled out withArchConstraints, archAddrWidth, and archEndianness
* added Arch module
* RISCV initialBlockRegs
* preliminary work on disassembleFn
* wip: disassembleFn
* made things more lens-y
* wip: disassemble instruction
* finished disassembly of grift assignment statements
* separated out DisInstM into separate module
* disassembly wip
* finished disassembleBlock
* Finished riscvDisassembleFn
* bump grift submodule
* made macaw discovery poly-kinded
* added risc-v test suite
* added risc-v test suite
* fixed macaw semantics to hardware x0 to constant value 0
* added riscvPreserveReg based on assembler's manual
* riscvDemandContext
* successfully disassembled a block!
* enhanced tests to allow optional entry point spec
* stubbed out identifyCall
* stubbed out identifyReturn
* passing initial test
* added checkForReturnAddr stub
* fleshed out identifyCall and identifyReturn
* update grift submodule
* bug fix and exception handling
* added EXC register, which tracks whether or not we've attempted to
read from/write to any system registers.
* Replaced custom CSR type with GRIFT's (but we're not using it
currently)
* added better show instance for GPRs we should migrate this to a
GRIFT pretty printer at some point)
* Fixed a vicious bug in the semantics; unsigned and signed LT were
getting swapped in translation
* added pattern synonyms for GPRs
* improved docs and fixed RISCVReg bug (GP was 3 instead of 4)
* changed undefineds to errors
* changed RISCV class to RISCVConstraints
* wrapped GRIFT's "RV" parameter in a type to remove the need to make
macaw architecture parameter polykinded
* rolled back all changes to macaw base that made things poly-kinded
* reverted two more macaw core changes, updated license, removed old PPC test
* macaw: update to upstream changes in bv-sized and grift
* address code review comments
* macaw-riscv: expose fewer modules
* Update RISCVTermStmt definition
* Update riscv_info. macaw-riscv now builds against master
* Update bv-sized and cabal freeze files
* Update cabal freeze files with satisfying lens version
* Get tests building
* Fix printf runtime error
* Add simpler tests
* Change RISCV target version and update grift pointer
[skip ci]
* Compressed branch test passes
[skip ci]
* Add additional small tests
[skip ci]
* Introduce a syscall PrimFn
* Syscalls now correctly classified
* Fix return regs from syscall
* Extract syscall arguments
* Update expected riscv test results
* Add macaw-riscv build + test to CI
* Get building with GHC 9.0.2
* Revert "Update cabal freeze files with satisfying lens version"
This reverts commit 4aa95c19c3.
* Install softfloat in CI
* Update Grift
* Some initial cleanup
* More cleanup
* Resolve FIXME on getReg
* Detect and only accept rv64gc rvreprs
* Address Tristan's PR comments
* Update Grift pointer
* Add info on installing Softfloat to README for macaw-riscv
* Add missing submodule step to softfloat build instructions
Co-authored-by: Ben Selfridge <benselfridge@000279.local>
Co-authored-by: Valentin Robert <val@galois.com>
49 lines
1.8 KiB
Plaintext
49 lines
1.8 KiB
Plaintext
|
|
function-call-rv64gc.exe: file format elf64-littleriscv
|
|
|
|
|
|
Disassembly of section .text:
|
|
|
|
000000000001010c <f2>:
|
|
1010c: 1101 c.addi sp,-32
|
|
1010e: ec22 c.sdsp s0,24(sp)
|
|
10110: 1000 c.addi4spn s0,sp,32
|
|
10112: 87aa c.mv a5,a0
|
|
10114: fef42623 sw a5,-20(s0)
|
|
10118: fec42783 lw a5,-20(s0)
|
|
1011c: 2785 c.addiw a5,1
|
|
1011e: 2781 c.addiw a5,0
|
|
10120: 853e c.mv a0,a5
|
|
10122: 6462 c.ldsp s0,24(sp)
|
|
10124: 6105 c.addi16sp sp,32
|
|
10126: 8082 c.jr ra
|
|
|
|
0000000000010128 <f1>:
|
|
10128: 1101 c.addi sp,-32
|
|
1012a: ec06 c.sdsp ra,24(sp)
|
|
1012c: e822 c.sdsp s0,16(sp)
|
|
1012e: 1000 c.addi4spn s0,sp,32
|
|
10130: 478d c.li a5,3
|
|
10132: fef42623 sw a5,-20(s0)
|
|
10136: fec42783 lw a5,-20(s0)
|
|
1013a: 853e c.mv a0,a5
|
|
1013c: fd1ff0ef jal ra,1010c <f2>
|
|
10140: 87aa c.mv a5,a0
|
|
10142: 853e c.mv a0,a5
|
|
10144: 60e2 c.ldsp ra,24(sp)
|
|
10146: 6442 c.ldsp s0,16(sp)
|
|
10148: 6105 c.addi16sp sp,32
|
|
1014a: 8082 c.jr ra
|
|
|
|
000000000001014c <_start>:
|
|
1014c: 1141 c.addi sp,-16
|
|
1014e: e406 c.sdsp ra,8(sp)
|
|
10150: e022 c.sdsp s0,0(sp)
|
|
10152: 0800 c.addi4spn s0,sp,16
|
|
10154: fd5ff0ef jal ra,10128 <f1>
|
|
10158: 0001 c.addi zero,0
|
|
1015a: 60a2 c.ldsp ra,8(sp)
|
|
1015c: 6402 c.ldsp s0,0(sp)
|
|
1015e: 0141 c.addi sp,16
|
|
10160: 8082 c.jr ra
|