Brett Boston a5796fc955 Reverse syscall override return register ordering (#284) ... When a user overrides a system call on an architecture that supports returning two values from a system call and they provide a context containing the result of the system call in the form ``` empty :> v0 :> v1 ``` macaw will perform the register assignment ``` r0 := v1 r1 := v0 ``` This change reverses this behavior so that the assignment becomes ``` r0 := v0 r1 := v1 ``` This brings the expected ordering of the result context in agreement with the left-to-right ordering of the argument context: ``` empty :> arg1 :> arg2 :> ... ```		2022-05-04 12:41:02 -07:00
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src/Data/Macaw	Reverse syscall override return register ordering (#284)	2022-05-04 12:41:02 -07:00
tests	Add RV32GC support to macaw-riscv (#269)	2022-03-21 14:08:50 -07:00
ChangeLog.md	Add RISC-V backend (#259)	2022-03-04 12:44:46 -08:00
LICENSE	Add RISC-V backend (#259)	2022-03-04 12:44:46 -08:00
macaw-riscv.cabal	Add RISC-V backend (#259)	2022-03-04 12:44:46 -08:00
Setup.hs	Add RISC-V backend (#259)	2022-03-04 12:44:46 -08:00