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This code accidentally included Cryptol type annotations in the Verilog output (because the `bv-sized` pretty-printer includes them). Hilariously, we didn't detect this because ABC can still correctly read the result due to its very permissive parser that skips over things it doesn't understand. Attempting to load files containing rotates into Yosys, which includes a stricter Verilog parser, uncovered the error. |
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.github/workflows | ||
dependencies | ||
what4 | ||
what4-abc | ||
what4-blt | ||
.gitignore | ||
.gitmodules | ||
.hlint.yaml | ||
cabal.project | ||
README.md |
What4 is a library for representing symbolic terms and communicating with satisfiability and SMT solvers (e.g. Yices and Z3).
It was originally a part of the Crucible project, but has found use cases that are independent of its original purpose as the representation language for the Crucible symbolic simulator, and has thus been split out into a separate repository.
For an overview of What4 and how to use it, please see the package-level README.
This material is based upon work supported by the Defense Advanced Research Projects Agency (DARPA) under Contract No. HR0011-19-C-0070. The views, opinions, and/or findings expressed are those of the author(s) and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.