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https://github.com/HigherOrderCO/Bend.git
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Add SHL and SHR
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parent
831e99e33e
commit
f4620bc3f6
4
Cargo.lock
generated
4
Cargo.lock
generated
@ -214,9 +214,9 @@ checksum = "809e18805660d7b6b2e2b9f316a5099521b5998d5cba4dda11b5157a21aaef03"
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[[package]]
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name = "hvm-core"
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version = "0.3.0-hvm32.compat.3"
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version = "0.3.0-hvm32.compat.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "4dc4ab0e7e0a79b299129792012b15085ff1d114bf3756f5e40269cecf2dd97a"
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checksum = "34f45b2e7a27af7ccecc60ee9c28f8c536c19dac677a0ddd0a19c382eb1367ee"
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dependencies = [
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"TSPL 0.0.9",
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"arrayvec",
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@ -26,7 +26,7 @@ cli = ["dep:clap"]
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TSPL = "0.0.12"
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clap = { version = "4.4.1", features = ["derive"], optional = true }
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highlight_error = "0.1.1"
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hvm-core = "=0.3.0-hvm32.compat.3"
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hvm-core = "=0.3.0-hvm32.compat.4"
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indexmap = "2.2.3"
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interner = "0.2.1"
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itertools = "0.11.0"
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@ -235,6 +235,8 @@ impl fmt::Display for Op {
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Op::OR => write!(f, "|"),
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Op::XOR => write!(f, "^"),
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Op::POW => write!(f, "**"),
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Op::SHR => write!(f, ">>"),
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Op::SHL => write!(f, "<<"),
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Op::LOG => todo!(),
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Op::ATN => todo!(),
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}
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@ -192,6 +192,8 @@ pub enum Op {
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AND,
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OR,
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XOR,
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SHL,
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SHR,
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/// atan(a, b)
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ATN,
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/// log_a(b)
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@ -907,9 +909,9 @@ impl Num {
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pub fn from_bits(bits: u32) -> Self {
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match get_typ(bits) {
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hvmc::ast::U24 => Num::U24(hvmc::ast::get_u24(bits)),
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hvmc::ast::I24 => Num::I24(hvmc::ast::get_i24(bits)),
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hvmc::ast::F24 => Num::F24(hvmc::ast::get_f24(bits)),
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hvmc::ast::TY_U24 => Num::U24(hvmc::ast::get_u24(bits)),
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hvmc::ast::TY_I24 => Num::I24(hvmc::ast::get_i24(bits)),
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hvmc::ast::TY_F24 => Num::F24(hvmc::ast::get_f24(bits)),
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_ => unreachable!("Invalid Num bits"),
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}
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}
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@ -224,7 +224,7 @@ impl Reader<'_> {
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let opr_node = self.net.enter_port(Port(port0_node, 0)).node();
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let opr_kind = self.net.node(opr_node).kind.clone();
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let opr = if let NodeKind::Num { val } = opr_kind {
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if get_typ(val) != hvmc::ast::SYM {
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if get_typ(val) != hvmc::ast::TY_SYM {
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self.error(ReadbackError::InvalidNumericOp);
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return Term::Err;
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}
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@ -479,10 +479,10 @@ impl Term {
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fn num_from_bits_with_type(val: u32, typ: u32) -> Term {
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match get_typ(typ) {
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// No type information, assume u24 by default
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hvmc::ast::SYM => Term::Num { val: Num::U24(get_u24(val)) },
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hvmc::ast::U24 => Term::Num { val: Num::U24(get_u24(val)) },
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hvmc::ast::I24 => Term::Num { val: Num::I24(get_i24(val)) },
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hvmc::ast::F24 => Term::Num { val: Num::F24(get_f24(val)) },
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hvmc::ast::TY_SYM => Term::Num { val: Num::U24(get_u24(val)) },
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hvmc::ast::TY_U24 => Term::Num { val: Num::U24(get_u24(val)) },
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hvmc::ast::TY_I24 => Term::Num { val: Num::I24(get_i24(val)) },
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hvmc::ast::TY_F24 => Term::Num { val: Num::F24(get_f24(val)) },
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_ => Term::Err,
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}
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}
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@ -1006,6 +1006,10 @@ pub trait ParserCommons<'a>: Parser<'a> {
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Op::DIV
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} else if self.try_consume_exactly("%") {
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Op::REM
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} else if self.try_consume_exactly("<<") {
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Op::SHL
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} else if self.try_consume_exactly(">>") {
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Op::SHR
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} else if self.try_consume_exactly("<") {
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Op::LT
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} else if self.try_consume_exactly(">") {
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@ -1039,6 +1043,10 @@ pub trait ParserCommons<'a>: Parser<'a> {
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Op::DIV
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} else if self.starts_with("%") {
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Op::REM
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} else if self.starts_with("<<") {
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Op::SHL
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} else if self.starts_with(">>") {
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Op::SHR
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} else if self.starts_with("<") {
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Op::LT
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} else if self.starts_with(">") {
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@ -423,22 +423,24 @@ fn hole<T: Default>() -> T {
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impl Op {
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fn to_native_tag(self) -> u32 {
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match self {
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Op::ADD => hvmc::ast::ADD,
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Op::SUB => hvmc::ast::SUB,
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Op::MUL => hvmc::ast::MUL,
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Op::DIV => hvmc::ast::DIV,
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Op::REM => hvmc::ast::REM,
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Op::EQ => hvmc::ast::EQ,
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Op::NEQ => hvmc::ast::NEQ,
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Op::LT => hvmc::ast::LT,
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Op::GT => hvmc::ast::GT,
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Op::AND => hvmc::ast::AND,
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Op::OR => hvmc::ast::OR,
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Op::XOR => hvmc::ast::XOR,
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Op::ADD => hvmc::ast::OP_ADD,
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Op::SUB => hvmc::ast::OP_SUB,
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Op::MUL => hvmc::ast::OP_MUL,
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Op::DIV => hvmc::ast::OP_DIV,
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Op::REM => hvmc::ast::OP_REM,
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Op::EQ => hvmc::ast::OP_EQ,
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Op::NEQ => hvmc::ast::OP_NEQ,
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Op::LT => hvmc::ast::OP_LT,
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Op::GT => hvmc::ast::OP_GT,
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Op::AND => hvmc::ast::OP_AND,
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Op::OR => hvmc::ast::OP_OR,
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Op::XOR => hvmc::ast::OP_XOR,
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Op::SHL => hvmc::ast::OP_SHL,
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Op::SHR => hvmc::ast::OP_SHR,
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Op::ATN => hvmc::ast::AND,
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Op::LOG => hvmc::ast::OR,
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Op::POW => hvmc::ast::XOR,
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Op::ATN => hvmc::ast::OP_AND,
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Op::LOG => hvmc::ast::OP_OR,
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Op::POW => hvmc::ast::OP_XOR,
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}
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}
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}
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@ -15,6 +15,10 @@ main = (List/expand
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(!= 20 10)
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(< 20 10)
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(> 20 10)
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#(<< 10 2)
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#(>> 10 2)
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0xFFFF
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(+ +20 +10)
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(- +20 +10)
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@ -29,6 +33,8 @@ main = (List/expand
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(< +20 +10)
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(> +20 +10)
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0xFFFF
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(+ -20 -10)
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(- -20 -10)
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(* -20 -10)
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@ -42,6 +48,8 @@ main = (List/expand
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(< -20 -10)
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(> -20 -10)
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0xFFFF
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(+ +20 -10)
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(- +20 -10)
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(* +20 -10)
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@ -55,6 +63,8 @@ main = (List/expand
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(< +20 -10)
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(> +20 -10)
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0xFFFF
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(+ -20 +10)
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(- -20 +10)
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(* -20 +10)
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@ -67,6 +77,8 @@ main = (List/expand
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(!= -20 +10)
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(< -20 +10)
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(> -20 +10)
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0xFFFF
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(+ +20.0 +10.0)
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(- +20.0 +10.0)
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@ -81,6 +93,8 @@ main = (List/expand
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(< +20.0 +10.0)
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(> +20.0 +10.0)
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0xFFFF
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(+ -20.0 -10.0)
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(- -20.0 -10.0)
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(* -20.0 -10.0)
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@ -94,6 +108,8 @@ main = (List/expand
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(< -20.0 -10.0)
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(> -20.0 -10.0)
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0xFFFF
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(+ +20.0 -10.0)
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(- +20.0 -10.0)
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(* +20.0 -10.0)
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@ -107,6 +123,8 @@ main = (List/expand
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(< +20.0 -10.0)
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(> +20.0 -10.0)
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0xFFFF
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(+ -20.0 +10.0)
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(- -20.0 +10.0)
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(* -20.0 +10.0)
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@ -3,7 +3,7 @@ source: tests/golden_tests.rs
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input_file: tests/golden_tests/run_file/basic_num_ops.bend
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---
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NumScott:
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[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]
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[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, 65535, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, 65535, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, 65535, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, 65535, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 65535, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, 65535, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 65535, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, 65535, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]
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Scott:
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[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]
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[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, 65535, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, 65535, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, 65535, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, 65535, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 65535, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, 65535, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 65535, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, 65535, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]
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