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Add SHL and SHR

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This commit is contained in:
Nicolas Abril 2024-05-21 17:32:13 +02:00
parent 831e99e33e
commit f4620bc3f6
9 changed files with 60 additions and 28 deletions
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4
Cargo.lock generated
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@ -214,9 +214,9 @@ checksum = "809e18805660d7b6b2e2b9f316a5099521b5998d5cba4dda11b5157a21aaef03"
[[package]]
name = "hvm-core"
version = "0.3.0-hvm32.compat.3"
version = "0.3.0-hvm32.compat.4"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "4dc4ab0e7e0a79b299129792012b15085ff1d114bf3756f5e40269cecf2dd97a"
checksum = "34f45b2e7a27af7ccecc60ee9c28f8c536c19dac677a0ddd0a19c382eb1367ee"
dependencies = [
"TSPL 0.0.9",
"arrayvec",

2
Cargo.toml
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@ -26,7 +26,7 @@ cli = ["dep:clap"]
TSPL = "0.0.12"
clap = { version = "4.4.1", features = ["derive"], optional = true }
highlight_error = "0.1.1"
hvm-core = "=0.3.0-hvm32.compat.3"
hvm-core = "=0.3.0-hvm32.compat.4"
indexmap = "2.2.3"
interner = "0.2.1"
itertools = "0.11.0"

2
src/fun/display.rs
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@ -235,6 +235,8 @@ impl fmt::Display for Op {
Op::OR => write!(f, "|"),
Op::XOR => write!(f, "^"),
Op::POW => write!(f, "**"),
Op::SHR => write!(f, ">>"),
Op::SHL => write!(f, "<<"),
Op::LOG => todo!(),
Op::ATN => todo!(),
}

8
src/fun/mod.rs
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@ -192,6 +192,8 @@ pub enum Op {
AND,
OR,
XOR,
SHL,
SHR,
/// atan(a, b)
ATN,
/// log_a(b)
@ -907,9 +909,9 @@ impl Num {
pub fn from_bits(bits: u32) -> Self {
match get_typ(bits) {
hvmc::ast::U24 => Num::U24(hvmc::ast::get_u24(bits)),
hvmc::ast::I24 => Num::I24(hvmc::ast::get_i24(bits)),
hvmc::ast::F24 => Num::F24(hvmc::ast::get_f24(bits)),
hvmc::ast::TY_U24 => Num::U24(hvmc::ast::get_u24(bits)),
hvmc::ast::TY_I24 => Num::I24(hvmc::ast::get_i24(bits)),
hvmc::ast::TY_F24 => Num::F24(hvmc::ast::get_f24(bits)),
_ => unreachable!("Invalid Num bits"),
}
}

10
src/fun/net_to_term.rs
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@ -224,7 +224,7 @@ impl Reader<'_> {
let opr_node = self.net.enter_port(Port(port0_node, 0)).node();
let opr_kind = self.net.node(opr_node).kind.clone();
let opr = if let NodeKind::Num { val } = opr_kind {
if get_typ(val) != hvmc::ast::SYM {
if get_typ(val) != hvmc::ast::TY_SYM {
self.error(ReadbackError::InvalidNumericOp);
return Term::Err;
}
@ -479,10 +479,10 @@ impl Term {
fn num_from_bits_with_type(val: u32, typ: u32) -> Term {
match get_typ(typ) {
// No type information, assume u24 by default
hvmc::ast::SYM => Term::Num { val: Num::U24(get_u24(val)) },
hvmc::ast::U24 => Term::Num { val: Num::U24(get_u24(val)) },
hvmc::ast::I24 => Term::Num { val: Num::I24(get_i24(val)) },
hvmc::ast::F24 => Term::Num { val: Num::F24(get_f24(val)) },
hvmc::ast::TY_SYM => Term::Num { val: Num::U24(get_u24(val)) },
hvmc::ast::TY_U24 => Term::Num { val: Num::U24(get_u24(val)) },
hvmc::ast::TY_I24 => Term::Num { val: Num::I24(get_i24(val)) },
hvmc::ast::TY_F24 => Term::Num { val: Num::F24(get_f24(val)) },
_ => Term::Err,
}
}

8
src/fun/parser.rs
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@ -1006,6 +1006,10 @@ pub trait ParserCommons<'a>: Parser<'a> {
Op::DIV
} else if self.try_consume_exactly("%") {
Op::REM
} else if self.try_consume_exactly("<<") {
Op::SHL
} else if self.try_consume_exactly(">>") {
Op::SHR
} else if self.try_consume_exactly("<") {
Op::LT
} else if self.try_consume_exactly(">") {
@ -1039,6 +1043,10 @@ pub trait ParserCommons<'a>: Parser<'a> {
Op::DIV
} else if self.starts_with("%") {
Op::REM
} else if self.starts_with("<<") {
Op::SHL
} else if self.starts_with(">>") {
Op::SHR
} else if self.starts_with("<") {
Op::LT
} else if self.starts_with(">") {

32
src/fun/term_to_net.rs
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@ -423,22 +423,24 @@ fn hole<T: Default>() -> T {
impl Op {
fn to_native_tag(self) -> u32 {
match self {
Op::ADD => hvmc::ast::ADD,
Op::SUB => hvmc::ast::SUB,
Op::MUL => hvmc::ast::MUL,
Op::DIV => hvmc::ast::DIV,
Op::REM => hvmc::ast::REM,
Op::EQ => hvmc::ast::EQ,
Op::NEQ => hvmc::ast::NEQ,
Op::LT => hvmc::ast::LT,
Op::GT => hvmc::ast::GT,
Op::AND => hvmc::ast::AND,
Op::OR => hvmc::ast::OR,
Op::XOR => hvmc::ast::XOR,
Op::ADD => hvmc::ast::OP_ADD,
Op::SUB => hvmc::ast::OP_SUB,
Op::MUL => hvmc::ast::OP_MUL,
Op::DIV => hvmc::ast::OP_DIV,
Op::REM => hvmc::ast::OP_REM,
Op::EQ => hvmc::ast::OP_EQ,
Op::NEQ => hvmc::ast::OP_NEQ,
Op::LT => hvmc::ast::OP_LT,
Op::GT => hvmc::ast::OP_GT,
Op::AND => hvmc::ast::OP_AND,
Op::OR => hvmc::ast::OP_OR,
Op::XOR => hvmc::ast::OP_XOR,
Op::SHL => hvmc::ast::OP_SHL,
Op::SHR => hvmc::ast::OP_SHR,
Op::ATN => hvmc::ast::AND,
Op::LOG => hvmc::ast::OR,
Op::POW => hvmc::ast::XOR,
Op::ATN => hvmc::ast::OP_AND,
Op::LOG => hvmc::ast::OP_OR,
Op::POW => hvmc::ast::OP_XOR,
}
}
}

18
tests/golden_tests/run_file/basic_num_ops.bend
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@ -15,6 +15,10 @@ main = (List/expand
(!= 20 10)
(< 20 10)
(> 20 10)
#(<< 10 2)
#(>> 10 2)
0xFFFF
(+ +20 +10)
(- +20 +10)
@ -29,6 +33,8 @@ main = (List/expand
(< +20 +10)
(> +20 +10)
0xFFFF
(+ -20 -10)
(- -20 -10)
(* -20 -10)
@ -42,6 +48,8 @@ main = (List/expand
(< -20 -10)
(> -20 -10)
0xFFFF
(+ +20 -10)
(- +20 -10)
(* +20 -10)
@ -55,6 +63,8 @@ main = (List/expand
(< +20 -10)
(> +20 -10)
0xFFFF
(+ -20 +10)
(- -20 +10)
(* -20 +10)
@ -67,6 +77,8 @@ main = (List/expand
(!= -20 +10)
(< -20 +10)
(> -20 +10)
0xFFFF
(+ +20.0 +10.0)
(- +20.0 +10.0)
@ -81,6 +93,8 @@ main = (List/expand
(< +20.0 +10.0)
(> +20.0 +10.0)
0xFFFF
(+ -20.0 -10.0)
(- -20.0 -10.0)
(* -20.0 -10.0)
@ -94,6 +108,8 @@ main = (List/expand
(< -20.0 -10.0)
(> -20.0 -10.0)
0xFFFF
(+ +20.0 -10.0)
(- +20.0 -10.0)
(* +20.0 -10.0)
@ -107,6 +123,8 @@ main = (List/expand
(< +20.0 -10.0)
(> +20.0 -10.0)
0xFFFF
(+ -20.0 +10.0)
(- -20.0 +10.0)
(* -20.0 +10.0)

4
tests/snapshots/run_file__basic_num_ops.bend.snap
View File

@ -3,7 +3,7 @@ source: tests/golden_tests.rs
input_file: tests/golden_tests/run_file/basic_num_ops.bend
---
NumScott:
[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]
[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, 65535, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, 65535, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, 65535, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, 65535, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 65535, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, 65535, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 65535, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, 65535, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]
Scott:
[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]
[30, 10, 200, 2, 0, 30, 0, 30, 0, 1, 0, 1, 65535, +30, +10, +200, +2, +0, +30, +0, +30, +0, +1, +0, +1, 65535, -30, -10, +200, +2, +0, +26, -28, -2, +0, +1, +1, +0, 65535, +10, +30, -200, -2, +0, -30, +20, -10, +0, +1, +0, +1, 65535, -10, -30, -200, -2, +0, -26, +8, -18, +0, +1, +1, +0, 65535, 30.000, 10.000, 200.000, 2.000, 0.000, 10240007340032.000, 1.107, 0.769, 0, 1, 0, 1, 65535, -30.000, -10.000, 200.000, 2.000, -0.000, 0.000, -2.034, NaN, 0, 1, 1, 0, 65535, 10.000, 30.000, -200.000, -2.000, 0.000, 0.000, 2.034, NaN, 0, 1, 0, 1, 65535, -10.000, -30.000, -200.000, -2.000, -0.000, 10240007340032.000, -1.107, NaN, 0, 1, 1, 0]