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parent
3525f7e0ca
commit
9d0ff9cf49
@ -5,14 +5,9 @@
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RLP.aux.0(
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add: Nat
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len: Nat
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H0: Either<Equal<Nat, add, 128>, Equal<Nat, add, 192>>
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pf0: Either<Equal<Nat, add, 128>, Equal<Nat, add, 192>>
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): Nat.ltn(0,Nat.add(add,len)) == Bool.true
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case H0 {
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} default
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case mirror(H0.value) {
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refl:
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refl
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}: Nat.ltn(0,Nat.add(self.b,len)) == Bool.true
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RLP.aux.0(add, len, pf0)
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// TODO: include `a <= 192`
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RLP.aux.1(
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