2020-01-18 11:38:21 +03:00
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/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2020-03-08 14:33:14 +03:00
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#include <AK/Memory.h>
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2019-07-13 21:15:17 +03:00
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#include <Kernel/Devices/SB16.h>
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#include <Kernel/Thread.h>
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2020-01-20 15:07:29 +03:00
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#include <Kernel/VM/AnonymousVMObject.h>
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2019-07-12 20:28:01 +03:00
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#include <Kernel/VM/MemoryManager.h>
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2020-02-09 17:47:15 +03:00
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#include <LibBareMetal/IO.h>
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2019-07-12 20:28:01 +03:00
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2019-07-13 18:08:45 +03:00
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//#define SB16_DEBUG
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2020-02-16 03:27:42 +03:00
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namespace Kernel {
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2020-02-22 21:19:13 +03:00
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#define SB16_DEFAULT_IRQ 5
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2020-02-16 03:27:42 +03:00
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2019-07-13 18:08:45 +03:00
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enum class SampleFormat : u8 {
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Signed = 0x10,
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Stereo = 0x20,
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};
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2019-07-12 20:28:01 +03:00
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const u16 DSP_READ = 0x22A;
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const u16 DSP_WRITE = 0x22C;
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const u16 DSP_STATUS = 0x22E;
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const u16 DSP_R_ACK = 0x22F;
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/* Write a value to the DSP write register */
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void SB16::dsp_write(u8 value)
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{
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while (IO::in8(DSP_WRITE) & 0x80) {
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;
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}
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IO::out8(DSP_WRITE, value);
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}
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/* Reads the value of the DSP read register */
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u8 SB16::dsp_read()
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{
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while (!(IO::in8(DSP_STATUS) & 0x80)) {
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;
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}
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return IO::in8(DSP_READ);
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}
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/* Changes the sample rate of sound output */
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void SB16::set_sample_rate(uint16_t hz)
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{
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dsp_write(0x41); // output
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dsp_write((u8)(hz >> 8));
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dsp_write((u8)hz);
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dsp_write(0x42); // input
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dsp_write((u8)(hz >> 8));
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dsp_write((u8)hz);
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}
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static SB16* s_the;
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SB16::SB16()
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2020-02-22 21:19:13 +03:00
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: IRQHandler(SB16_DEFAULT_IRQ)
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2019-07-12 20:28:01 +03:00
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, CharacterDevice(42, 42) // ### ?
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{
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s_the = this;
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initialize();
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}
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SB16::~SB16()
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{
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}
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SB16& SB16::the()
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{
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return *s_the;
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}
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void SB16::initialize()
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{
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2020-01-23 00:23:50 +03:00
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disable_irq();
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2019-12-01 14:53:19 +03:00
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2019-07-12 20:28:01 +03:00
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IO::out8(0x226, 1);
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IO::delay();
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IO::out8(0x226, 0);
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auto data = dsp_read();
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if (data != 0xaa) {
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2020-03-01 22:45:39 +03:00
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klog() << "SB16: sb not ready";
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2019-07-12 20:28:01 +03:00
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return;
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}
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// Get the version info
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dsp_write(0xe1);
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m_major_version = dsp_read();
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auto vmin = dsp_read();
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2020-03-01 22:45:39 +03:00
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klog() << "SB16: found version " << m_major_version << "." << vmin;
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2020-02-22 21:19:13 +03:00
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set_irq_register(SB16_DEFAULT_IRQ);
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2020-03-01 22:45:39 +03:00
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klog() << "SB16: IRQ " << get_irq_line();
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2020-02-22 21:19:13 +03:00
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}
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void SB16::set_irq_register(u8 irq_number)
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{
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u8 bitmask;
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switch (irq_number) {
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case 2:
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bitmask = 0;
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break;
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case 5:
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bitmask = 0b10;
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break;
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case 7:
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bitmask = 0b100;
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break;
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case 10:
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bitmask = 0b1000;
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break;
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default:
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ASSERT_NOT_REACHED();
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}
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IO::out8(0x224, 0x80);
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IO::out8(0x225, bitmask);
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}
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u8 SB16::get_irq_line()
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{
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IO::out8(0x224, 0x80);
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u8 bitmask = IO::in8(0x225);
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switch (bitmask) {
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case 0:
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return 2;
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case 0b10:
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return 5;
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case 0b100:
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return 7;
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case 0b1000:
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return 10;
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}
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return bitmask;
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}
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void SB16::set_irq_line(u8 irq_number)
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{
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InterruptDisabler disabler;
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if (irq_number == get_irq_line())
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return;
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set_irq_register(irq_number);
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change_irq_number(irq_number);
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2019-07-12 20:28:01 +03:00
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}
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2019-11-04 16:03:14 +03:00
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bool SB16::can_read(const FileDescription&) const
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2019-07-12 20:28:01 +03:00
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{
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return false;
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}
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ssize_t SB16::read(FileDescription&, u8*, ssize_t)
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{
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return 0;
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}
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void SB16::dma_start(uint32_t length)
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{
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2020-01-20 15:07:29 +03:00
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const auto addr = m_dma_region->vmobject().physical_pages()[0]->paddr().get();
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2019-07-13 18:08:45 +03:00
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const u8 channel = 5; // 16-bit samples use DMA channel 5 (on the master DMA controller)
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2019-07-12 20:28:01 +03:00
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const u8 mode = 0;
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// Disable the DMA channel
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2019-07-13 18:08:45 +03:00
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IO::out8(0xd4, 4 + (channel % 4));
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2019-07-12 20:28:01 +03:00
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// Clear the byte pointer flip-flop
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2019-07-13 18:08:45 +03:00
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IO::out8(0xd8, 0);
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2019-07-12 20:28:01 +03:00
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// Write the DMA mode for the transfer
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2019-07-13 18:08:45 +03:00
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IO::out8(0xd6, (channel % 4) | mode);
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2019-07-12 20:28:01 +03:00
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// Write the offset of the buffer
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2019-07-13 22:28:35 +03:00
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u16 offset = (addr / 2) % 65536;
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IO::out8(0xc4, (u8)offset);
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IO::out8(0xc4, (u8)(offset >> 8));
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2019-07-12 20:28:01 +03:00
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// Write the transfer length
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2019-07-13 18:08:45 +03:00
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IO::out8(0xc6, (u8)(length - 1));
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IO::out8(0xc6, (u8)((length - 1) >> 8));
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2019-07-12 20:28:01 +03:00
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// Write the buffer
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2019-07-13 18:08:45 +03:00
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IO::out8(0x8b, addr >> 16);
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2019-07-12 20:28:01 +03:00
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// Enable the DMA channel
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2019-07-13 18:08:45 +03:00
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IO::out8(0xd4, (channel % 4));
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2019-07-12 20:28:01 +03:00
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}
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2020-02-22 21:19:13 +03:00
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void SB16::handle_irq(RegisterState&)
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2019-07-14 16:02:02 +03:00
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{
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// Stop sound output ready for the next block.
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dsp_write(0xd5);
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IO::in8(DSP_STATUS); // 8 bit interrupt
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if (m_major_version >= 4)
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IO::in8(DSP_R_ACK); // 16 bit interrupt
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2019-12-01 14:53:19 +03:00
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m_irq_queue.wake_all();
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2019-07-14 16:02:02 +03:00
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}
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2019-07-12 20:28:01 +03:00
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void SB16::wait_for_irq()
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{
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2020-02-17 17:04:27 +03:00
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Thread::current->wait_on(m_irq_queue);
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2020-01-23 00:23:50 +03:00
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disable_irq();
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2019-07-12 20:28:01 +03:00
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}
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ssize_t SB16::write(FileDescription&, const u8* data, ssize_t length)
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{
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2020-01-20 15:07:29 +03:00
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if (!m_dma_region) {
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auto page = MM.allocate_supervisor_physical_page();
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auto vmobject = AnonymousVMObject::create_with_physical_page(*page);
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m_dma_region = MM.allocate_kernel_region_with_vmobject(*vmobject, PAGE_SIZE, "SB16 DMA buffer", Region::Access::Write);
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}
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2019-07-12 20:28:01 +03:00
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2019-07-13 18:55:39 +03:00
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#ifdef SB16_DEBUG
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2020-03-01 22:45:39 +03:00
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klog() << "SB16: Writing buffer of " << length << " bytes";
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2019-07-13 18:55:39 +03:00
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#endif
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2019-07-13 18:08:45 +03:00
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ASSERT(length <= PAGE_SIZE);
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2019-07-12 20:28:01 +03:00
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const int BLOCK_SIZE = 32 * 1024;
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if (length > BLOCK_SIZE) {
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return -ENOSPC;
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}
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2019-07-13 18:08:45 +03:00
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2019-07-13 18:51:18 +03:00
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u8 mode = (u8)SampleFormat::Signed | (u8)SampleFormat::Stereo;
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2019-07-12 20:28:01 +03:00
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const int sample_rate = 44100;
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set_sample_rate(sample_rate);
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2020-01-20 15:07:29 +03:00
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memcpy(m_dma_region->vaddr().as_ptr(), data, length);
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2019-07-13 18:08:45 +03:00
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dma_start(length);
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2019-07-12 20:28:01 +03:00
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2019-07-13 22:28:35 +03:00
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// 16-bit single-cycle output.
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// FIXME: Implement auto-initialized output.
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u8 command = 0xb0;
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2019-07-12 20:28:01 +03:00
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2019-07-13 18:47:57 +03:00
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u16 sample_count = length / sizeof(i16);
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if (mode & (u8)SampleFormat::Stereo)
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sample_count /= 2;
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sample_count -= 1;
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2020-03-06 04:22:53 +03:00
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cli();
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enable_irq();
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2019-07-12 20:28:01 +03:00
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dsp_write(command);
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dsp_write(mode);
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2019-07-13 18:47:57 +03:00
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dsp_write((u8)sample_count);
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dsp_write((u8)(sample_count >> 8));
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2019-07-12 20:28:01 +03:00
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wait_for_irq();
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return length;
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}
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2020-02-16 03:27:42 +03:00
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}
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