From 04a912f68fa6e0fa529e480e74d12e287a62c850 Mon Sep 17 00:00:00 2001
From: Gunnar Beutner <gbeutner@serenityos.org>
Date: Sat, 3 Jul 2021 00:25:41 +0200
Subject: [PATCH] Kernel: Hide the implementation detail that MSRs use two
 registers

When retrieving and setting x86 MSRs two registers are required. The
existing setter and getter for the MSR class made this implementation
detail visible to the caller. This changes the setter and getter to
use u64 instead.
---
 Kernel/Arch/x86/MSR.h                | 8 ++++++--
 Kernel/Arch/x86/common/Processor.cpp | 2 +-
 Kernel/Interrupts/APIC.cpp           | 9 +++------
 3 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/Kernel/Arch/x86/MSR.h b/Kernel/Arch/x86/MSR.h
index 462390467e3..4638b81c592 100644
--- a/Kernel/Arch/x86/MSR.h
+++ b/Kernel/Arch/x86/MSR.h
@@ -30,15 +30,19 @@ public:
     {
     }
 
-    void get(u32& low, u32& high)
+    [[nodiscard]] u64 get()
     {
+        u32 low, high;
         asm volatile("rdmsr"
                      : "=a"(low), "=d"(high)
                      : "c"(m_msr));
+        return ((u64)high << 32) | low;
     }
 
-    void set(u32 low, u32 high)
+    void set(u64 value)
     {
+        u32 low = value & 0xffffffff;
+        u32 high = value >> 32;
         asm volatile("wrmsr" ::"a"(low), "d"(high), "c"(m_msr));
     }
 };
diff --git a/Kernel/Arch/x86/common/Processor.cpp b/Kernel/Arch/x86/common/Processor.cpp
index 652aa051443..90a2b3af3bc 100644
--- a/Kernel/Arch/x86/common/Processor.cpp
+++ b/Kernel/Arch/x86/common/Processor.cpp
@@ -1128,7 +1128,7 @@ UNMAP_AFTER_INIT void Processor::gdt_init()
 
 #if ARCH(X86_64)
     MSR gs_base(MSR_GS_BASE);
-    gs_base.set((size_t)this & 0xffffffff, (size_t)this >> 32);
+    gs_base.set((u64)this);
 #else
     asm volatile(
         "mov %%ax, %%ds\n"
diff --git a/Kernel/Interrupts/APIC.cpp b/Kernel/Interrupts/APIC.cpp
index fe8de2a2c8b..d56743e8de0 100644
--- a/Kernel/Interrupts/APIC.cpp
+++ b/Kernel/Interrupts/APIC.cpp
@@ -136,18 +136,15 @@ UNMAP_AFTER_INIT void APIC::initialize()
 
 PhysicalAddress APIC::get_base()
 {
-    u32 lo, hi;
     MSR msr(APIC_BASE_MSR);
-    msr.get(lo, hi);
-    return PhysicalAddress(lo & 0xfffff000);
+    auto base = msr.get();
+    return PhysicalAddress(base & 0xfffff000);
 }
 
 void APIC::set_base(const PhysicalAddress& base)
 {
-    u32 hi = 0;
-    u32 lo = base.get() | 0x800;
     MSR msr(APIC_BASE_MSR);
-    msr.set(lo, hi);
+    msr.set(base.get() | 0x800);
 }
 
 void APIC::write_register(u32 offset, u32 value)