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Kernel: Introduce stages in Aarch64 CPU initialization phase
Dropping to each exception level is now more explicit.
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parent
c08f059340
commit
0f81fb03f2
Notes:
sideshowbarker
2024-07-19 16:59:04 +09:00
Author: https://github.com/konradekk Commit: https://github.com/SerenityOS/serenity/commit/0f81fb03f2b Pull-request: https://github.com/SerenityOS/serenity/pull/16781 Reviewed-by: https://github.com/ADKaster ✅ Reviewed-by: https://github.com/gmta
@ -68,7 +68,7 @@ inline void wait_cycles(int n)
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}
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}
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inline void el1_vector_table_install(void* vector_table)
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inline void load_el1_vector_table(void* vector_table)
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{
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asm("msr VBAR_EL1, %[value]" ::[value] "r"(vector_table));
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}
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@ -6,9 +6,11 @@
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#pragma once
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#include <AK/Types.h>
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namespace Kernel {
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void drop_to_exception_level_1();
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void initialize_exceptions(u32 cpu);
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void init_page_tables();
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}
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@ -9,9 +9,11 @@
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#include <Kernel/Arch/aarch64/Registers.h>
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#include <Kernel/Panic.h>
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extern "C" uintptr_t vector_table_el1;
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namespace Kernel {
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static void drop_to_el2()
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static void drop_el3_to_el2()
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{
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Aarch64::SCR_EL3 secure_configuration_register_el3 = {};
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@ -40,7 +42,7 @@ static void drop_to_el2()
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Aarch64::Asm::enter_el2_from_el3();
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}
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static void drop_to_el1()
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static void drop_el2_to_el1()
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{
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Aarch64::HCR_EL2 hypervisor_configuration_register_el2 = {};
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hypervisor_configuration_register_el2.RW = 1; // EL1 to use 64-bit mode
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@ -64,7 +66,7 @@ static void drop_to_el1()
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Aarch64::Asm::enter_el1_from_el2();
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}
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static void set_up_el1()
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static void setup_el1()
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{
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Aarch64::SCTLR_EL1 system_control_register_el1 = Aarch64::SCTLR_EL1::reset_value();
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@ -78,24 +80,34 @@ static void set_up_el1()
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system_control_register_el1.A = 1; // Enable memory access alignment check
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Aarch64::SCTLR_EL1::write(system_control_register_el1);
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Aarch64::Asm::load_el1_vector_table(&vector_table_el1);
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}
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void drop_to_exception_level_1()
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void initialize_exceptions(u32 cpu)
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{
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switch (Aarch64::Asm::get_current_exception_level()) {
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case Aarch64::Asm::ExceptionLevel::EL3:
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drop_to_el2();
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[[fallthrough]];
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case Aarch64::Asm::ExceptionLevel::EL2:
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drop_to_el1();
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[[fallthrough]];
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case Aarch64::Asm::ExceptionLevel::EL1:
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set_up_el1();
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break;
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default: {
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PANIC("CPU booted in unsupported exception mode!");
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auto base_exception_level = Aarch64::Asm::get_current_exception_level();
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if (base_exception_level > Aarch64::Asm::ExceptionLevel::EL3) {
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PANIC("CPU[{}]: Started in unknown EL{}", cpu, static_cast<u8>(base_exception_level));
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} else if (base_exception_level < Aarch64::Asm::ExceptionLevel::EL1) {
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PANIC("CPU[{}]: Started in unsupported EL{}", cpu, static_cast<u8>(base_exception_level));
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} else {
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dbgln("CPU[{}]: Started in EL{}", cpu, static_cast<u8>(base_exception_level));
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}
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if (base_exception_level > Aarch64::Asm::ExceptionLevel::EL2) {
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drop_el3_to_el2();
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dbgln("CPU[{}]: Dropped to EL2", cpu);
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}
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if (base_exception_level > Aarch64::Asm::ExceptionLevel::EL1) {
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drop_el2_to_el1();
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dbgln("CPU[{}]: Dropped to EL1", cpu);
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}
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setup_el1();
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dbgln("CPU[{}]: Set up EL1", cpu);
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}
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}
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@ -18,8 +18,6 @@
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#include <Kernel/Thread.h>
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#include <Kernel/Time/TimeManagement.h>
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extern "C" uintptr_t vector_table_el1;
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namespace Kernel {
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extern "C" void thread_context_first_enter(void);
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@ -33,14 +31,7 @@ void Processor::initialize(u32 cpu)
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{
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VERIFY(g_current_processor == nullptr);
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auto current_exception_level = static_cast<u64>(Aarch64::Asm::get_current_exception_level());
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dbgln("CPU{} started in: EL{}", cpu, current_exception_level);
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dbgln("Drop CPU{} to EL1", cpu);
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drop_to_exception_level_1();
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// Load EL1 vector table
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Aarch64::Asm::el1_vector_table_install(&vector_table_el1);
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initialize_exceptions(cpu);
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g_current_processor = this;
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}
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