diff --git a/Kernel/Arch/riscv64/Interrupts.cpp b/Kernel/Arch/riscv64/Interrupts.cpp
index babc7b091a6..96c25223034 100644
--- a/Kernel/Arch/riscv64/Interrupts.cpp
+++ b/Kernel/Arch/riscv64/Interrupts.cpp
@@ -60,7 +60,8 @@ extern "C" void trap_handler(TrapFrame& trap_frame)
         // Exception
 
         Processor::current().enter_trap(trap_frame, false);
-        Processor::enable_interrupts();
+        if (trap_frame.regs->sstatus.SPIE == 1)
+            Processor::enable_interrupts();
 
         using enum RISCV64::CSR::SCAUSE;
         switch (scause) {