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Kernel: Move IO delay code to x86 architecture subdirectory
Many code patterns and hardware procedures rely on reliable delay in the microseconds granularity, and since they are using such delays which are valid cases, but should not rely on x86 specific code, we allow to determine in compile time the proper platform-specific code to use to invoke such delays.
This commit is contained in:
parent
cac72259d0
commit
84fbab6803
Notes:
sideshowbarker
2024-07-17 06:48:12 +09:00
Author: https://github.com/supercomputer7 Commit: https://github.com/SerenityOS/serenity/commit/84fbab6803 Pull-request: https://github.com/SerenityOS/serenity/pull/15173 Reviewed-by: https://github.com/linusg
15
Kernel/Arch/Delay.h
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15
Kernel/Arch/Delay.h
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Types.h>
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namespace Kernel {
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void microseconds_delay(u32 microseconds);
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}
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17
Kernel/Arch/x86/common/Delay.cpp
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17
Kernel/Arch/x86/common/Delay.cpp
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@ -0,0 +1,17 @@
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/*
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* Copyright (c) 2022, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Arch/x86/IO.h>
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namespace Kernel {
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void microseconds_delay(u32 microseconds)
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{
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IO::delay(microseconds);
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}
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}
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@ -6,6 +6,7 @@
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*/
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#include <AK/Platform.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Bus/USB/UHCI/UHCIController.h>
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#include <Kernel/Bus/USB/USBRequest.h>
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@ -633,7 +634,7 @@ void UHCIController::reset_port(u8 port)
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// Wait at least 50 ms for the port to reset.
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// This is T DRSTR in the USB 2.0 Specification Page 186 Table 7-13.
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constexpr u16 reset_delay = 50 * 1000;
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IO::delay(reset_delay);
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microseconds_delay(reset_delay);
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port_data &= ~UHCI_PORTSC_PORT_RESET;
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if (port == 0)
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@ -644,7 +645,7 @@ void UHCIController::reset_port(u8 port)
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// Wait 10 ms for the port to recover.
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// This is T RSTRCY in the USB 2.0 Specification Page 188 Table 7-14.
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constexpr u16 reset_recovery_delay = 10 * 1000;
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IO::delay(reset_recovery_delay);
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microseconds_delay(reset_recovery_delay);
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port_data = port == 0 ? read_portsc1() : read_portsc2();
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port_data |= UHCI_PORTSC_PORT_ENABLED;
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Bus/USB/USBClasses.h>
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#include <Kernel/Bus/USB/USBController.h>
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@ -83,7 +84,7 @@ ErrorOr<void> Hub::enumerate_and_power_on_hub()
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}
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// Wait for the ports to power up. power_on_to_power_good_time is in units of 2 ms and we want in us, so multiply by 2000.
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IO::delay(descriptor.power_on_to_power_good_time * 2000);
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microseconds_delay(descriptor.power_on_to_power_good_time * 2000);
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memcpy(&m_hub_descriptor, &descriptor, sizeof(USBHubDescriptor));
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@ -171,7 +172,7 @@ void Hub::check_for_port_updates()
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// FIXME: Timeout
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while (debounce_timer < debounce_interval) {
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IO::delay(debounce_disconnect_check_interval);
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microseconds_delay(debounce_disconnect_check_interval);
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debounce_timer += debounce_disconnect_check_interval;
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if (auto result = get_port_status(port_number, port_status); result.is_error()) {
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@ -203,7 +204,7 @@ void Hub::check_for_port_updates()
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// Wait at least 10 ms for the port to reset.
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// This is T DRST in the USB 2.0 Specification Page 186 Table 7-13.
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constexpr u16 reset_delay = 10 * 1000;
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IO::delay(reset_delay);
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microseconds_delay(reset_delay);
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if (auto result = get_port_status(port_number, port_status); result.is_error()) {
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dbgln("USB Hub: Error occurred when getting status while resetting port {}: {}.", port_number, result.error());
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@ -224,7 +225,7 @@ void Hub::check_for_port_updates()
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// Wait 10 ms for the port to recover.
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// This is T RSTRCY in the USB 2.0 Specification Page 188 Table 7-14.
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constexpr u16 reset_recovery_delay = 10 * 1000;
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IO::delay(reset_recovery_delay);
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microseconds_delay(reset_recovery_delay);
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dbgln_if(USB_DEBUG, "USB Hub: Reset complete!");
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@ -333,6 +333,7 @@ if ("${SERENITY_ARCH}" STREQUAL "i686" OR "${SERENITY_ARCH}" STREQUAL "x86_64")
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${KERNEL_SOURCES}
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Arch/Processor.cpp
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Arch/x86/common/Delay.cpp
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Arch/x86/common/I8042Reboot.cpp
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Arch/x86/common/ScopedCritical.cpp
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Arch/x86/common/SmapDisabler.cpp
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@ -5,6 +5,7 @@
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*/
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#include <AK/Format.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Devices/Audio/AC97.h>
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#include <Kernel/Devices/DeviceManagement.h>
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#include <Kernel/Memory/AnonymousVMObject.h>
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@ -291,7 +292,7 @@ void AC97::AC97Channel::reset()
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control_register.out(AudioControlRegisterFlag::ResetRegisters);
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while ((control_register.in<u8>() & AudioControlRegisterFlag::ResetRegisters) > 0)
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IO::delay(50);
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microseconds_delay(50);
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m_dma_running.with([](auto& dma_running) {
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dma_running = false;
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Devices/HID/I8042Controller.h>
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#include <Kernel/Devices/HID/PS2KeyboardDevice.h>
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@ -71,7 +72,7 @@ UNMAP_AFTER_INIT bool I8042Controller::check_existence_via_probing(Badge<HIDMana
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break;
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}
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// Note: Wait 500 microseconds in case the controller couldn't respond
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IO::delay(500);
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microseconds_delay(500);
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}
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if (!successful_self_test) {
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dbgln("I8042: Trying to probe for existence of controller failed");
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@ -246,7 +247,7 @@ ErrorOr<void> I8042Controller::drain_output_buffer()
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return {};
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IO::in8(I8042Port::Buffer);
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IO::delay(100);
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microseconds_delay(100);
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}
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return Error::from_errno(EBUSY);
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}
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@ -332,14 +333,14 @@ ErrorOr<void> I8042Controller::prepare_for_input(HIDDevice::Type device)
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for (int attempt = 0; attempt < 1000; attempt++) {
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u8 status = IO::in8(I8042Port::Status);
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if (!(status & I8042StatusFlag::OutputBuffer)) {
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IO::delay(1000);
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microseconds_delay(1000);
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continue;
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}
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if (device == HIDDevice::Type::Unknown)
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return {};
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if ((status & I8042StatusFlag::SecondPS2PortOutputBuffer) == second_port_flag)
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return {};
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IO::delay(1000);
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microseconds_delay(1000);
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}
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return Error::from_errno(EBUSY);
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}
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@ -351,7 +352,7 @@ ErrorOr<void> I8042Controller::prepare_for_output()
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u8 status = IO::in8(I8042Port::Status);
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if (!(status & I8042StatusFlag::InputBuffer))
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return {};
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IO::delay(1000);
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microseconds_delay(1000);
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}
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return Error::from_errno(EBUSY);
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}
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@ -5,6 +5,7 @@
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*/
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#include <AK/Singleton.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Bus/PCI/IDs.h>
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@ -46,7 +47,7 @@ void GraphicsManagement::disable_vga_emulation_access_permanently()
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IO::out8(0x3c4, 1);
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u8 sr1 = IO::in8(0x3c5);
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IO::out8(0x3c5, sr1 | 1 << 5);
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IO::delay(1000);
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microseconds_delay(1000);
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m_vga_access_is_disabled = true;
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}
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Debug.h>
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#include <Kernel/Devices/DeviceManagement.h>
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@ -371,7 +371,7 @@ bool IntelNativeDisplayConnector::gmbus_wait_for(IntelGraphics::GMBusStatus desi
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default:
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VERIFY_NOT_REACHED();
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}
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IO::delay(1000);
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microseconds_delay(1000);
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milliseconds_passed++;
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}
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}
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@ -544,7 +544,7 @@ void IntelNativeDisplayConnector::set_display_timings(Graphics::Modesetting cons
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dbgln_if(INTEL_GRAPHICS_DEBUG, "sourceSize - {}, {}", (modesetting.vertical.active - 1), (modesetting.horizontal.active - 1));
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write_to_register(IntelGraphics::RegisterIndex::PipeASource, (modesetting.vertical.active - 1) | (modesetting.horizontal.active - 1) << 16);
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IO::delay(200);
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microseconds_delay(200);
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}
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bool IntelNativeDisplayConnector::wait_for_enabled_pipe_a(size_t milliseconds_timeout) const
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@ -553,7 +553,7 @@ bool IntelNativeDisplayConnector::wait_for_enabled_pipe_a(size_t milliseconds_ti
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while (current_time < milliseconds_timeout) {
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if (pipe_a_enabled())
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return true;
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IO::delay(1000);
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microseconds_delay(1000);
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current_time++;
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}
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return false;
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@ -564,7 +564,7 @@ bool IntelNativeDisplayConnector::wait_for_disabled_pipe_a(size_t milliseconds_t
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while (current_time < milliseconds_timeout) {
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if (!pipe_a_enabled())
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return true;
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IO::delay(1000);
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microseconds_delay(1000);
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current_time++;
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}
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return false;
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@ -576,7 +576,7 @@ bool IntelNativeDisplayConnector::wait_for_disabled_pipe_b(size_t milliseconds_t
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while (current_time < milliseconds_timeout) {
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if (!pipe_b_enabled())
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return true;
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IO::delay(1000);
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microseconds_delay(1000);
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current_time++;
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}
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return false;
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@ -662,14 +662,14 @@ void IntelNativeDisplayConnector::enable_dpll_without_vga(IntelGraphics::PLLSett
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set_dpll_registers(settings);
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IO::delay(200);
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microseconds_delay(200);
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write_to_register(IntelGraphics::RegisterIndex::DPLLControlA, (6 << 9) | (settings.p1) << 16 | (1 << 26) | (1 << 28) | (1 << 31));
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write_to_register(IntelGraphics::RegisterIndex::DPLLMultiplierA, (dac_multiplier - 1) | ((dac_multiplier - 1) << 8));
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// The specification says we should wait (at least) about 150 microseconds
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// after enabling the DPLL to allow the clock to stabilize
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IO::delay(200);
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microseconds_delay(200);
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VERIFY(read_from_register(IntelGraphics::RegisterIndex::DPLLControlA) & (1 << 31));
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}
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@ -8,7 +8,7 @@
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#include <AK/Memory.h>
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#include <AK/Singleton.h>
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#include <AK/Types.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Arch/x86/MSR.h>
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#include <Kernel/Arch/x86/ProcessorInfo.h>
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#include <Kernel/Debug.h>
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@ -186,7 +186,7 @@ void APIC::set_siv(u32 offset, u8 interrupt)
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void APIC::wait_for_pending_icr()
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{
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while ((read_register(APIC_REG_ICR_LOW) & APIC_ICR_DELIVERY_PENDING) != 0) {
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IO::delay(200);
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microseconds_delay(200);
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}
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}
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@ -409,13 +409,13 @@ UNMAP_AFTER_INIT void APIC::do_boot_aps()
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// INIT
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write_icr({ 0, 0, ICRReg::INIT, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf });
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IO::delay(10 * 1000);
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microseconds_delay(10 * 1000);
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for (int i = 0; i < 2; i++) {
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// SIPI
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write_icr({ 0x08, 0, ICRReg::StartUp, ICRReg::Physical, ICRReg::Assert, ICRReg::TriggerMode::Edge, ICRReg::AllExcludingSelf }); // start execution at P8000
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IO::delay(200);
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microseconds_delay(200);
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}
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// Now wait until the ap_cpu_init_pending variable dropped to 0, which means all APs are initialized and no longer need these special mappings
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@ -423,7 +423,7 @@ UNMAP_AFTER_INIT void APIC::do_boot_aps()
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dbgln_if(APIC_DEBUG, "APIC: Waiting for {} AP(s) to finish initialization...", aps_to_enable);
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do {
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// Wait a little bit
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IO::delay(200);
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microseconds_delay(200);
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} while (m_apic_ap_count.load(AK::MemoryOrder::memory_order_consume) != aps_to_enable);
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}
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@ -537,7 +537,7 @@ UNMAP_AFTER_INIT void APIC::init_finished(u32 cpu)
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// we don't want APs to trigger IPIs (e.g. through MM) while the BSP
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// is unable to process them
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while (!m_apic_ap_continue.load(AK::MemoryOrder::memory_order_consume)) {
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IO::delay(200);
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microseconds_delay(200);
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}
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dbgln_if(APIC_DEBUG, "APIC: CPU #{} continues, all others are initialized", cpu);
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@ -4,8 +4,9 @@
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/Format.h>
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#include <AK/Time.h>
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/CMOS.h>
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#include <Kernel/RTC.h>
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@ -43,7 +44,7 @@ static bool try_to_read_registers(unsigned& year, unsigned& month, unsigned& day
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update_in_progress_ended_successfully = true;
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break;
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}
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IO::delay(1000);
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microseconds_delay(1000);
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time_passed_in_milliseconds++;
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}
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@ -8,6 +8,7 @@
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#include <AK/BuiltinWrappers.h>
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#include <AK/OwnPtr.h>
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#include <AK/Types.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/CommandLine.h>
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#include <Kernel/Library/LockRefPtr.h>
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@ -42,7 +43,7 @@ bool AHCIController::reset()
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return false;
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if (!(hba().control_regs.ghc & 1))
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break;
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IO::delay(1000);
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microseconds_delay(1000);
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retry++;
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}
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// Note: Turn on AHCI HBA and Global HBA Interrupts.
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@ -8,6 +8,7 @@
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// please look at Documentation/Kernel/AHCILocking.md
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#include <AK/Atomic.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Locking/Spinlock.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Memory/ScatterGatherList.h>
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@ -552,7 +553,7 @@ bool AHCIPort::spin_until_ready() const
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size_t spin = 0;
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dbgln_if(AHCI_DEBUG, "AHCI Port {}: Spinning until ready.", representative_port_index());
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while ((m_port_registers.tfd & (ATA_SR_BSY | ATA_SR_DRQ)) && spin <= 100) {
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IO::delay(1000);
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microseconds_delay(1000);
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spin++;
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}
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if (spin == 100) {
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@ -719,7 +720,7 @@ bool AHCIPort::identify_device()
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success = true;
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break;
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}
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IO::delay(1000); // delay with 1 milliseconds
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microseconds_delay(1000); // delay with 1 milliseconds
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time_elapsed++;
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}
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@ -739,7 +740,7 @@ void AHCIPort::wait_until_condition_met_or_timeout(size_t delay_in_microseconds,
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while (retry < retries) {
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if (condition_being_met())
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break;
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IO::delay(delay_in_microseconds);
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microseconds_delay(delay_in_microseconds);
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retry++;
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}
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}
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@ -852,7 +853,7 @@ bool AHCIPort::initiate_sata_reset()
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full_memory_barrier();
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set_interface_state(AHCI::DeviceDetectionInitialization::PerformInterfaceInitializationSequence);
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// The AHCI specification says to wait now a 1 millisecond
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IO::delay(1000);
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microseconds_delay(1000);
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full_memory_barrier();
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set_interface_state(AHCI::DeviceDetectionInitialization::NoActionRequested);
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full_memory_barrier();
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@ -4,7 +4,7 @@
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <Kernel/Arch/x86/IO.h>
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#include <Kernel/Arch/Delay.h>
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#include <Kernel/Storage/ATA/ATADiskDevice.h>
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#include <Kernel/Storage/ATA/ATAPort.h>
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#include <Kernel/Storage/ATA/Definitions.h>
|
||||
@ -499,7 +499,7 @@ ErrorOr<void> ATAPort::execute_polled_command(TransactionDirection direction, LB
|
||||
break;
|
||||
}
|
||||
|
||||
IO::delay(1000);
|
||||
microseconds_delay(1000);
|
||||
milliseconds_elapsed++;
|
||||
}
|
||||
if (milliseconds_elapsed > completion_timeout_in_milliseconds) {
|
||||
|
@ -7,6 +7,7 @@
|
||||
#include <AK/ByteBuffer.h>
|
||||
#include <AK/Singleton.h>
|
||||
#include <AK/StringView.h>
|
||||
#include <Kernel/Arch/Delay.h>
|
||||
#include <Kernel/Arch/x86/IO.h>
|
||||
#include <Kernel/Bus/PCI/API.h>
|
||||
#include <Kernel/Memory/MemoryManager.h>
|
||||
@ -44,13 +45,13 @@ StringView IDEChannel::channel_type_string() const
|
||||
|
||||
bool IDEChannel::select_device_and_wait_until_not_busy(DeviceType device_type, size_t milliseconds_timeout)
|
||||
{
|
||||
IO::delay(20);
|
||||
microseconds_delay(20);
|
||||
u8 slave = device_type == DeviceType::Slave;
|
||||
m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xA0 | (slave << 4)); // First, we need to select the drive itself
|
||||
IO::delay(20);
|
||||
microseconds_delay(20);
|
||||
size_t time_elapsed = 0;
|
||||
while (m_io_group.control_base().in<u8>() & ATA_SR_BSY && time_elapsed <= milliseconds_timeout) {
|
||||
IO::delay(1000);
|
||||
microseconds_delay(1000);
|
||||
time_elapsed++;
|
||||
}
|
||||
return time_elapsed <= milliseconds_timeout;
|
||||
@ -63,10 +64,10 @@ ErrorOr<void> IDEChannel::port_phy_reset()
|
||||
// reset the channel
|
||||
u8 device_control = m_io_group.control_base().in<u8>();
|
||||
// Wait 30 milliseconds
|
||||
IO::delay(30000);
|
||||
microseconds_delay(30000);
|
||||
m_io_group.control_base().out<u8>(device_control | (1 << 2));
|
||||
// Wait 30 milliseconds
|
||||
IO::delay(30000);
|
||||
microseconds_delay(30000);
|
||||
m_io_group.control_base().out<u8>(device_control);
|
||||
// Wait up to 30 seconds before failing
|
||||
if (!select_device_and_wait_until_not_busy(DeviceType::Master, 30000)) {
|
||||
@ -220,7 +221,7 @@ ErrorOr<void> IDEChannel::wait_if_busy_until_timeout(size_t timeout_in_milliseco
|
||||
{
|
||||
size_t time_elapsed = 0;
|
||||
while (m_io_group.control_base().in<u8>() & ATA_SR_BSY && time_elapsed <= timeout_in_milliseconds) {
|
||||
IO::delay(1000);
|
||||
microseconds_delay(1000);
|
||||
time_elapsed++;
|
||||
}
|
||||
if (time_elapsed <= timeout_in_milliseconds)
|
||||
@ -249,7 +250,7 @@ ErrorOr<void> IDEChannel::load_taskfile_into_registers(ATAPort::TaskFile const&
|
||||
// Note: Preserve the selected drive, always use LBA addressing
|
||||
auto driver_register = ((m_io_group.io_base().offset(ATA_REG_HDDEVSEL).in<u8>() & (1 << 4)) | (head | (1 << 5) | (1 << 6)));
|
||||
m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(driver_register);
|
||||
IO::delay(50);
|
||||
microseconds_delay(50);
|
||||
|
||||
if (lba_mode == LBAMode::FortyEightBit) {
|
||||
m_io_group.io_base().offset(ATA_REG_SECCOUNT1).out<u8>((task_file.count >> 8) & 0xFF);
|
||||
@ -272,7 +273,7 @@ ErrorOr<void> IDEChannel::load_taskfile_into_registers(ATAPort::TaskFile const&
|
||||
auto status = m_io_group.control_base().in<u8>();
|
||||
if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
|
||||
break;
|
||||
IO::delay(1000);
|
||||
microseconds_delay(1000);
|
||||
time_elapsed++;
|
||||
}
|
||||
m_io_group.io_base().offset(ATA_REG_COMMAND).out<u8>(task_file.command);
|
||||
@ -284,9 +285,9 @@ ErrorOr<void> IDEChannel::device_select(size_t device_index)
|
||||
VERIFY(m_lock.is_locked());
|
||||
if (device_index > 1)
|
||||
return Error::from_errno(EINVAL);
|
||||
IO::delay(20);
|
||||
microseconds_delay(20);
|
||||
m_io_group.io_base().offset(ATA_REG_HDDEVSEL).out<u8>(0xA0 | ((device_index) << 4));
|
||||
IO::delay(20);
|
||||
microseconds_delay(20);
|
||||
return {};
|
||||
}
|
||||
|
||||
|
@ -7,9 +7,8 @@
|
||||
|
||||
#include <AK/Format.h>
|
||||
#include <AK/Types.h>
|
||||
#include <Kernel/Arch/Delay.h>
|
||||
#include <Kernel/Arch/SafeMem.h>
|
||||
#include <Kernel/Arch/x86/IO.h>
|
||||
#include <Kernel/Arch/x86/Processor.h>
|
||||
#include <Kernel/Bus/PCI/API.h>
|
||||
#include <Kernel/CommandLine.h>
|
||||
#include <Kernel/Devices/Device.h>
|
||||
@ -77,7 +76,7 @@ bool NVMeController::wait_for_ready(bool expected_ready_bit_value)
|
||||
|
||||
u32 expected_rdy = expected_ready_bit_value ? 1 : 0;
|
||||
while (((m_controller_regs->csts >> CSTS_RDY_BIT) & 0x1) != expected_rdy) {
|
||||
IO::delay(one_ms_io_delay);
|
||||
microseconds_delay(one_ms_io_delay);
|
||||
|
||||
if (--wait_iterations == 0) {
|
||||
if (((m_controller_regs->csts >> CSTS_RDY_BIT) & 0x1) != expected_rdy) {
|
||||
|
@ -4,7 +4,7 @@
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*/
|
||||
|
||||
#include <Kernel/Arch/x86/IO.h>
|
||||
#include <Kernel/Arch/Delay.h>
|
||||
#include <Kernel/Devices/BlockDevice.h>
|
||||
#include <Kernel/Storage/NVMe/NVMeDefinitions.h>
|
||||
#include <Kernel/Storage/NVMe/NVMePollQueue.h>
|
||||
@ -20,7 +20,7 @@ void NVMePollQueue::submit_sqe(NVMeSubmission& sub)
|
||||
NVMeQueue::submit_sqe(sub);
|
||||
SpinlockLocker lock_cq(m_cq_lock);
|
||||
while (!process_cq()) {
|
||||
IO::delay(1);
|
||||
microseconds_delay(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -4,7 +4,7 @@
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*/
|
||||
|
||||
#include <Kernel/Arch/x86/IO.h>
|
||||
#include <Kernel/Arch/Delay.h>
|
||||
#include <Kernel/StdLib.h>
|
||||
#include <Kernel/Storage/NVMe/NVMeController.h>
|
||||
#include <Kernel/Storage/NVMe/NVMeInterruptQueue.h>
|
||||
@ -126,7 +126,7 @@ u16 NVMeQueue::submit_sync_sqe(NVMeSubmission& sub)
|
||||
index = m_qdepth - 1;
|
||||
}
|
||||
cqe_cid = m_cqe_array[index].command_id;
|
||||
IO::delay(1);
|
||||
microseconds_delay(1);
|
||||
} while (cid != cqe_cid);
|
||||
|
||||
auto status = CQ_STATUS_FIELD(m_cqe_array[m_cq_head].status);
|
||||
|
@ -7,6 +7,7 @@
|
||||
*/
|
||||
|
||||
#include <AK/StdLibExtras.h>
|
||||
#include <Kernel/Arch/Delay.h>
|
||||
#include <Kernel/CommandLine.h>
|
||||
#include <Kernel/Debug.h>
|
||||
#include <Kernel/Devices/DeviceManagement.h>
|
||||
@ -327,7 +328,7 @@ void VirtualConsole::beep()
|
||||
if (!kernel_command_line().is_pc_speaker_enabled())
|
||||
return;
|
||||
PCSpeaker::tone_on(440);
|
||||
IO::delay(10000);
|
||||
microseconds_delay(10000);
|
||||
PCSpeaker::tone_off();
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user