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Kernel: Detect and store the virtual address bit width during CPU init
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parent
d872f0d503
commit
cd975668d6
Notes:
sideshowbarker
2024-07-18 03:03:33 +09:00
Author: https://github.com/IdanHo Commit: https://github.com/SerenityOS/serenity/commit/cd975668d6d Pull-request: https://github.com/SerenityOS/serenity/pull/10361
@ -129,6 +129,7 @@ class Processor {
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CPUFeature m_features;
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static Atomic<u32> g_total_processors;
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u8 m_physical_address_bit_width;
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u8 m_virtual_address_bit_width;
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ProcessorInfo* m_info;
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Thread* m_current_thread;
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@ -253,6 +254,7 @@ public:
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}
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ALWAYS_INLINE u8 physical_address_bit_width() const { return m_physical_address_bit_width; }
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ALWAYS_INLINE u8 virtual_address_bit_width() const { return m_virtual_address_bit_width; }
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ALWAYS_INLINE ProcessorInfo& info() { return *m_info; }
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@ -138,9 +138,13 @@ UNMAP_AFTER_INIT void Processor::cpu_detect()
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// CPUID.80000008H:EAX[7:0] reports the physical-address width supported by the processor.
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CPUID cpuid(0x80000008);
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m_physical_address_bit_width = cpuid.eax() & 0xff;
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// CPUID.80000008H:EAX[15:8] reports the linear-address width supported by the processor.
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m_virtual_address_bit_width = (cpuid.eax() >> 8) & 0xff;
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} else {
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// For processors that do not support CPUID function 80000008H, the width is generally 36 if CPUID.01H:EDX.PAE [bit 6] = 1 and 32 otherwise.
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m_physical_address_bit_width = has_feature(CPUFeature::PAE) ? 36 : 32;
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// Processors that do not support CPUID function 80000008H, support a linear-address width of 32.
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m_virtual_address_bit_width = 32;
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}
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CPUID extended_features(0x7);
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@ -335,6 +339,7 @@ UNMAP_AFTER_INIT void Processor::initialize(u32 cpu)
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if (!has_feature(CPUFeature::RDRAND))
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dmesgln("CPU[{}]: No RDRAND support detected, randomness will be poor", current_id());
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dmesgln("CPU[{}]: Physical address bit width: {}", current_id(), m_physical_address_bit_width);
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dmesgln("CPU[{}]: Virtual address bit width: {}", current_id(), m_virtual_address_bit_width);
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if (cpu == 0)
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idt_init();
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