diff --git a/Kernel/Storage/NVMe/NVMeController.cpp b/Kernel/Storage/NVMe/NVMeController.cpp index 51c78449375..681fbbfc77a 100644 --- a/Kernel/Storage/NVMe/NVMeController.cpp +++ b/Kernel/Storage/NVMe/NVMeController.cpp @@ -45,7 +45,7 @@ ErrorOr NVMeController::initialize() // Map only until doorbell register for the controller // Queues will individually map the doorbell register respectively - m_controller_regs = Memory::map_typed_writable(PhysicalAddress(m_bar)); + m_controller_regs = Memory::map_typed_writable(PhysicalAddress(m_bar)); calculate_doorbell_stride(); TRY(create_admin_queue(irq)); @@ -250,7 +250,7 @@ ErrorOr NVMeController::create_admin_queue(u8 irq) auto buffer = TRY(MM.allocate_dma_buffer_pages(sq_size, "Admin SQ queue", Memory::Region::Access::ReadWrite, sq_dma_pages)); sq_dma_region = move(buffer); } - auto doorbell_regs = Memory::map_typed_writable(PhysicalAddress(m_bar + REG_SQ0TDBL_START)); + auto doorbell_regs = Memory::map_typed_writable(PhysicalAddress(m_bar + REG_SQ0TDBL_START)); m_admin_queue = TRY(NVMeQueue::try_create(0, irq, qdepth, move(cq_dma_region), cq_dma_pages, move(sq_dma_region), sq_dma_pages, move(doorbell_regs))); @@ -317,7 +317,7 @@ ErrorOr NVMeController::create_io_queue(u8 irq, u8 qid) } auto queue_doorbell_offset = REG_SQ0TDBL_START + ((2 * qid) * (4 << m_dbl_stride)); - auto doorbell_regs = Memory::map_typed_writable(PhysicalAddress(m_bar + queue_doorbell_offset)); + auto doorbell_regs = Memory::map_typed_writable(PhysicalAddress(m_bar + queue_doorbell_offset)); m_queues.append(TRY(NVMeQueue::try_create(qid, irq, IO_QUEUE_SIZE, move(cq_dma_region), cq_dma_pages, move(sq_dma_region), sq_dma_pages, move(doorbell_regs)))); m_queues.last().enable_interrupts(); diff --git a/Kernel/Storage/NVMe/NVMeController.h b/Kernel/Storage/NVMe/NVMeController.h index af41444b1ec..3ac08eb7ca4 100644 --- a/Kernel/Storage/NVMe/NVMeController.h +++ b/Kernel/Storage/NVMe/NVMeController.h @@ -69,7 +69,7 @@ private: RefPtr m_admin_queue; NonnullRefPtrVector m_queues; NonnullRefPtrVector m_namespaces; - Memory::TypedMapping m_controller_regs; + Memory::TypedMapping m_controller_regs; bool m_admin_queue_ready { false }; size_t m_device_count {}; u32 m_bar; diff --git a/Kernel/Storage/NVMe/NVMeQueue.cpp b/Kernel/Storage/NVMe/NVMeQueue.cpp index 0c7dd1e99b3..dfe46325e48 100644 --- a/Kernel/Storage/NVMe/NVMeQueue.cpp +++ b/Kernel/Storage/NVMe/NVMeQueue.cpp @@ -13,14 +13,14 @@ namespace Kernel { -ErrorOr> NVMeQueue::try_create(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs) +ErrorOr> NVMeQueue::try_create(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs) { auto queue = TRY(adopt_nonnull_ref_or_enomem(new (nothrow) NVMeQueue(qid, irq, q_depth, move(cq_dma_region), cq_dma_page, move(sq_dma_region), sq_dma_page, move(db_regs)))); TRY(queue->create()); return queue; } -NVMeQueue::NVMeQueue(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs) +NVMeQueue::NVMeQueue(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs) : IRQHandler(irq) , m_qid(qid) , m_admin_queue(qid == 0) diff --git a/Kernel/Storage/NVMe/NVMeQueue.h b/Kernel/Storage/NVMe/NVMeQueue.h index 40ba9ffd836..b95ea6cf5d0 100644 --- a/Kernel/Storage/NVMe/NVMeQueue.h +++ b/Kernel/Storage/NVMe/NVMeQueue.h @@ -29,9 +29,9 @@ class AsyncBlockDeviceRequest; class NVMeQueue : public IRQHandler , public RefCounted { public: - static ErrorOr> try_create(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs); + static ErrorOr> try_create(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs); ErrorOr create(); - explicit NVMeQueue(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs); + explicit NVMeQueue(u16 qid, u8 irq, u32 q_depth, OwnPtr cq_dma_region, NonnullRefPtrVector cq_dma_page, OwnPtr sq_dma_region, NonnullRefPtrVector sq_dma_page, Memory::TypedMapping db_regs); bool is_admin_queue() { return m_admin_queue; }; bool handle_irq(const RegisterState&) override; void submit_sqe(struct NVMeSubmission&); @@ -73,7 +73,7 @@ private: NonnullRefPtrVector m_sq_dma_page; Span m_cqe_array; OwnPtr m_rw_dma_region; - Memory::TypedMapping m_db_regs; + Memory::TypedMapping m_db_regs; RefPtr m_rw_dma_page; Spinlock m_request_lock; RefPtr m_current_request;