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Kernel: Add helpers for manipulating x86 control registers
Use read_cr{0,2,3,4} and write_cr{0,3,4} helpers instead of inline asm.
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parent
8d0b744ebb
commit
da100f12a6
Notes:
sideshowbarker
2024-07-18 22:08:58 +09:00
Author: https://github.com/awesomekling Commit: https://github.com/SerenityOS/serenity/commit/da100f12a6a
@ -149,18 +149,7 @@ static void dump(const RegisterState& regs)
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dbgln(" ds={:04x} es={:04x} fs={:04x} gs={:04x}", (u16)regs.ds, (u16)regs.es, (u16)regs.fs, (u16)regs.gs);
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dbgln(" eax={:08x} ebx={:08x} ecx={:08x} edx={:08x}", regs.eax, regs.ebx, regs.ecx, regs.edx);
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dbgln(" ebp={:08x} esp={:08x} esi={:08x} edi={:08x}", regs.ebp, regs.esp, regs.esi, regs.edi);
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u32 cr0;
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asm("movl %%cr0, %%eax"
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: "=a"(cr0));
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u32 cr2;
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asm("movl %%cr2, %%eax"
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: "=a"(cr2));
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u32 cr3 = read_cr3();
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u32 cr4;
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asm("movl %%cr4, %%eax"
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: "=a"(cr4));
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dbgln(" cr0={:08x} cr2={:08x} cr3={:08x} cr4={:08x}", cr0, cr2, cr3, cr4);
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dbgln(" cr0={:08x} cr2={:08x} cr3={:08x} cr4={:08x}", read_cr0(), read_cr2(), read_cr3(), read_cr4());
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}
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void handle_crash(RegisterState& regs, const char* description, int signal, bool out_of_memory)
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@ -364,20 +353,11 @@ void breakpoint_handler(TrapFrame* trap)
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current_thread->send_urgent_signal_to_self(SIGTRAP);
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}
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#define EH(i, msg) \
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static void _exception##i() \
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{ \
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dbgln("{}", msg); \
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u32 cr0, cr2, cr3, cr4; \
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asm("movl %%cr0, %%eax" \
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: "=a"(cr0)); \
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asm("movl %%cr2, %%eax" \
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: "=a"(cr2)); \
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asm("movl %%cr3, %%eax" \
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: "=a"(cr3)); \
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asm("movl %%cr4, %%eax" \
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: "=a"(cr4)); \
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PANIC("cr0={:08x} cr2={:08x} cr3={:08x} cr4={:08x}", cr0, cr2, cr3, cr4); \
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#define EH(i, msg) \
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static void _exception##i() \
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{ \
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dbgln("{}", msg); \
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PANIC("cr0={:08x} cr2={:08x} cr3={:08x} cr4={:08x}", read_cr0(), read_cr2(), read_cr3(), read_cr4()); \
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}
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EH(2, "Unknown error")
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@ -733,16 +713,20 @@ void exit_trap(TrapFrame* trap)
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return Processor::current().exit_trap(*trap);
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}
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void write_cr0(u32 value)
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{
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asm volatile("movl %%eax, %%cr0" ::"a"(value));
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}
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void write_cr4(u32 value)
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{
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asm volatile("movl %%eax, %%cr4" ::"a"(value));
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}
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static void sse_init()
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{
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asm volatile(
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"mov %cr0, %eax\n"
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"andl $0xfffffffb, %eax\n"
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"orl $0x2, %eax\n"
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"mov %eax, %cr0\n"
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"mov %cr4, %eax\n"
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"orl $0x600, %eax\n"
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"mov %eax, %cr4\n");
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write_cr0((read_cr0() & 0xfffffffbu) | 0x2);
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write_cr4(read_cr4() | 0x600);
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}
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u32 read_cr0()
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@ -753,6 +737,14 @@ u32 read_cr0()
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return cr0;
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}
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u32 read_cr2()
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{
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u32 cr2;
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asm("movl %%cr2, %%eax"
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: "=a"(cr2));
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return cr2;
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}
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u32 read_cr3()
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{
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u32 cr3;
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@ -911,18 +903,11 @@ void Processor::cpu_setup()
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if (has_feature(CPUFeature::SSE))
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sse_init();
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asm volatile(
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"movl %%cr0, %%eax\n"
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"orl $0x00010000, %%eax\n"
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"movl %%eax, %%cr0\n" ::
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: "%eax", "memory");
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write_cr0(read_cr0() | 0x00010000);
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if (has_feature(CPUFeature::PGE)) {
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// Turn on CR4.PGE so the CPU will respect the G bit in page tables.
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asm volatile(
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"mov %cr4, %eax\n"
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"orl $0x80, %eax\n"
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"mov %eax, %cr4\n");
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write_cr4(read_cr4() | 0x80);
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}
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if (has_feature(CPUFeature::NX)) {
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@ -936,32 +921,20 @@ void Processor::cpu_setup()
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if (has_feature(CPUFeature::SMEP)) {
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// Turn on CR4.SMEP
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asm volatile(
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"mov %cr4, %eax\n"
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"orl $0x100000, %eax\n"
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"mov %eax, %cr4\n");
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write_cr4(read_cr4() | 0x100000);
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}
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if (has_feature(CPUFeature::SMAP)) {
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// Turn on CR4.SMAP
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asm volatile(
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"mov %cr4, %eax\n"
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"orl $0x200000, %eax\n"
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"mov %eax, %cr4\n");
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write_cr4(read_cr4() | 0x200000);
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}
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if (has_feature(CPUFeature::UMIP)) {
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asm volatile(
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"mov %cr4, %eax\n"
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"orl $0x800, %eax\n"
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"mov %eax, %cr4\n");
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write_cr4(read_cr4() | 0x800);
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}
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if (has_feature(CPUFeature::TSC)) {
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asm volatile(
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"mov %cr4, %eax\n"
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"orl $0x4, %eax\n"
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"mov %eax, %cr4\n");
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write_cr4(read_cr4() | 0x4);
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}
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}
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@ -526,10 +526,14 @@ inline FlatPtr offset_in_page(const void* address)
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}
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u32 read_cr0();
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u32 read_cr2();
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u32 read_cr3();
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void write_cr3(u32);
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u32 read_cr4();
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void write_cr0(u32);
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void write_cr3(u32);
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void write_cr4(u32);
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u32 read_dr6();
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static inline bool is_kernel_mode()
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