From e7d4bbcde87e02cc51db4d7edc6fd8a451278522 Mon Sep 17 00:00:00 2001 From: konrad Date: Sat, 24 Dec 2022 01:19:35 +0100 Subject: [PATCH] Kernel: Add MIDR_EL1, Main ID Register This register is already provided in a separate class but will be migrated here for uniform access --- Kernel/Arch/aarch64/Registers.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Kernel/Arch/aarch64/Registers.h b/Kernel/Arch/aarch64/Registers.h index 411eeb6e02d..fbd3db62592 100644 --- a/Kernel/Arch/aarch64/Registers.h +++ b/Kernel/Arch/aarch64/Registers.h @@ -311,6 +311,28 @@ struct alignas(u64) SCTLR_EL1 { }; static_assert(sizeof(SCTLR_EL1) == 8); +// https://developer.arm.com/documentation/ddi0601/2022-09/AArch64-Registers/MIDR-EL1--Main-ID-Register?lang=en +// MIDR_EL1, Main ID Register +struct alignas(u64) MIDR_EL1 { + int Revision : 4; + int PartNum : 12; + int Architecture : 4; + int Variant : 4; + int Implementer : 8; + int : 32; + + static inline MIDR_EL1 read() + { + MIDR_EL1 affinity_register; + + asm("mrs %[value], MIDR_EL1" + : [value] "=r"(affinity_register)); + + return affinity_register; + } +}; +static_assert(sizeof(MIDR_EL1) == 8); + // https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/HCR-EL2--Hypervisor-Configuration-Register // Hypervisor Configuration Register struct alignas(u64) HCR_EL2 {