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The hierarchy is AHCIController, AHCIPortHandler, AHCIPort and SATADiskDevice. Each AHCIController has at least one AHCIPortHandler. An AHCIPortHandler is an interrupt handler that takes care of enumeration of handled AHCI ports when an interrupt occurs. Each AHCIPort takes care of one SATADiskDevice, and later on we can add support for Port multiplier. When we implement support of Message signalled interrupts, we can spawn many AHCIPortHandlers, and allow each one of them to be responsible for a set of AHCIPorts.
94 lines
3.6 KiB
C++
94 lines
3.6 KiB
C++
/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include <AK/OwnPtr.h>
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#include <AK/RefPtr.h>
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#include <Kernel/Devices/Device.h>
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#include <Kernel/IO.h>
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#include <Kernel/Interrupts/IRQHandler.h>
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#include <Kernel/Lock.h>
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#include <Kernel/PhysicalAddress.h>
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#include <Kernel/Random.h>
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#include <Kernel/Storage/AHCIController.h>
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#include <Kernel/Storage/AHCIPort.h>
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#include <Kernel/Storage/StorageDevice.h>
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#include <Kernel/VM/PhysicalPage.h>
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#include <Kernel/WaitQueue.h>
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namespace Kernel {
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class AsyncBlockDeviceRequest;
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class AHCIController;
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class AHCIPort;
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class AHCIPortHandler final : public RefCounted<AHCIPortHandler>
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, public IRQHandler {
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friend class AHCIController;
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friend class SATADiskDevice;
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public:
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UNMAP_AFTER_INIT static NonnullRefPtr<AHCIPortHandler> create(AHCIController&, u8 irq, AHCI::MaskedBitField taken_ports);
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virtual ~AHCIPortHandler() override;
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RefPtr<StorageDevice> device_at_port(size_t port_index) const;
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virtual const char* purpose() const override { return "SATA Port Handler"; }
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AHCI::HBADefinedCapabilities hba_capabilities() const;
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NonnullRefPtr<AHCIController> hba_controller() const { return m_parent_controller; }
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PhysicalAddress get_identify_metadata_physical_region(u32 port_index) const;
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bool is_responsible_for_port_index(u32 port_index) const { return m_taken_ports.is_set_at(port_index); }
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private:
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UNMAP_AFTER_INIT AHCIPortHandler(AHCIController&, u8 irq, AHCI::MaskedBitField taken_ports);
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//^ IRQHandler
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virtual void handle_irq(const RegisterState&) override;
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enum class Direction : u8 {
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Read,
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Write,
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};
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AHCI::MaskedBitField create_pending_ports_interrupts_bitfield() const;
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void start_request(AsyncBlockDeviceRequest&, bool, bool, u16);
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void complete_current_request(AsyncDeviceRequest::RequestResult);
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void enumerate_ports(Function<void(const AHCIPort&)> callback) const;
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RefPtr<AHCIPort> port_at_index(u32 port_index) const;
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// Data members
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HashMap<u32, NonnullRefPtr<AHCIPort>> m_handled_ports;
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NonnullRefPtr<AHCIController> m_parent_controller;
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NonnullRefPtrVector<PhysicalPage> m_identify_metadata_pages;
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AHCI::MaskedBitField m_taken_ports;
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AHCI::MaskedBitField m_pending_ports_interrupts;
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};
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}
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