mirror of
https://github.com/LadybirdBrowser/ladybird.git
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3d4afe7614
I've wasted a silly amount of time in the past fretting over which of these words to use. Let's just choose one and use it everywhere. :^)
433 lines
13 KiB
C++
433 lines
13 KiB
C++
/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <AK/Types.h>
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namespace Kernel::FIS {
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enum class Type : u8 {
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RegisterHostToDevice = 0x27,
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RegisterDeviceToHost = 0x34,
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DMAActivate = 0x39,
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DMASetup = 0x41,
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Data = 0x46,
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BISTActivate = 0x58,
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PIOSetup = 0x5F,
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SetDeviceBits = 0xA1
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};
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enum class DwordCount : size_t {
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RegisterHostToDevice = 5,
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RegisterDeviceToHost = 5,
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DMAActivate = 1,
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DMASetup = 7,
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PIOSetup = 5,
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SetDeviceBits = 2
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};
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enum HeaderAttributes : u8 {
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C = (1 << 7), /* Updates Command register */
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};
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struct [[gnu::packed]] Header {
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u8 fis_type;
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u8 port_muliplier;
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};
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}
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namespace Kernel::FIS::HostToDevice {
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struct [[gnu::packed]] Register {
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Header header;
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u8 command;
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u8 features_low;
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u8 lba_low[3];
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u8 device;
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u8 lba_high[3];
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u8 features_high;
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u16 count;
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u8 icc; /* Isochronous Command Completion */
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u8 control;
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u32 reserved;
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};
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};
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namespace Kernel::FIS::DeviceToHost {
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struct [[gnu::packed]] Register {
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Header header;
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u8 status;
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u8 error;
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u8 lba_low[3];
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u8 device;
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u8 lba_high[3];
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u8 reserved;
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u16 count;
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u8 reserved2[6];
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};
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struct [[gnu::packed]] SetDeviceBits {
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Header header;
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u8 status;
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u8 error;
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u32 protocol_specific;
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};
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struct [[gnu::packed]] DMAActivate {
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Header header;
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u16 reserved;
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};
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struct [[gnu::packed]] PIOSetup {
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Header header;
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u8 status;
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u8 error;
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u8 lba_low[3];
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u8 device;
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u8 lba_high[3];
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u8 reserved;
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u16 count;
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u8 reserved2;
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u8 e_status;
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u16 transfer_count;
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u16 reserved3;
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};
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}
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namespace Kernel::FIS::BiDirectional {
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struct [[gnu::packed]] Data {
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Header header;
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u16 reserved;
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u32 data[];
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};
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struct [[gnu::packed]] BISTActivate {
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};
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struct [[gnu::packed]] DMASetup {
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Header header;
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u16 reserved;
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u32 dma_buffer_identifier_low;
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u32 dma_buffer_identifier_high;
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u32 reserved2;
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u32 dma_buffer_offset;
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u32 dma_transfer_count;
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u32 reserved3;
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};
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}
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namespace Kernel::AHCI {
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class MaskedBitField {
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public:
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explicit MaskedBitField(volatile u32& bitfield_register)
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: m_bitfield(bitfield_register)
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, m_bit_mask(0xffffffff)
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{
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}
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MaskedBitField(volatile u32& bitfield_register, u32 bit_mask)
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: m_bitfield(bitfield_register)
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, m_bit_mask(bit_mask)
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{
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}
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void set_at(u8 index) const
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{
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VERIFY(((1 << index) & m_bit_mask) != 0);
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m_bitfield = m_bitfield | ((1 << index) & m_bit_mask);
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}
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void set_all() const
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{
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m_bitfield = m_bitfield | (0xffffffff & m_bit_mask);
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}
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bool is_set_at(u32 port_index) const
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{
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return m_bitfield & ((1 << port_index) & m_bit_mask);
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}
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Vector<u8> to_vector() const
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{
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// FIXME: Add a sync mechanism!
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Vector<u8> indices;
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u32 bitfield = m_bitfield & m_bit_mask;
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for (size_t index = 0; index < 32; index++) {
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if (bitfield & 1) {
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indices.append(index);
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}
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bitfield >>= 1;
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}
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return indices;
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}
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u32 bit_mask() const { return m_bit_mask; };
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// Disable default implementations that would use surprising integer promotion.
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bool operator==(const MaskedBitField&) const = delete;
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bool operator<=(const MaskedBitField&) const = delete;
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bool operator>=(const MaskedBitField&) const = delete;
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bool operator<(const MaskedBitField&) const = delete;
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bool operator>(const MaskedBitField&) const = delete;
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private:
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volatile u32& m_bitfield;
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const u32 m_bit_mask;
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};
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enum Limits : u16 {
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MaxPorts = 32,
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MaxCommands = 32,
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MaxMultiplierConnectedPorts = 16,
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};
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enum CommandHeaderAttributes : u16 {
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C = (1 << 10), /* Clear Busy upon R_OK */
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P = (1 << 7), /* Prefetchable */
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W = (1 << 6), /* Write */
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A = (1 << 5), /* ATAPI */
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R = (1 << 8) /* Reset */
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};
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enum HBACapabilities : u32 {
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S64A = (u32)1 << 31, /* Supports 64-bit Addressing */
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SNCQ = 1 << 30, /* Supports Native Command Queuing */
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SSNTF = 1 << 29, /* Supports SNotification Register */
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SMPS = 1 << 28, /* Supports Mechanical Presence Switch */
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SSS = 1 << 27, /* Supports Staggered Spin-up */
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SALP = 1 << 26, /* Supports Aggressive Link Power Management */
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SAL = 1 << 25, /* Supports Activity LED */
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SCLO = 1 << 24, /* Supports Command List Override */
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SAM = 1 << 18, /* Supports AHCI mode only */
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SPM = 1 << 17, /* Supports Port Multiplier */
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FBSS = 1 << 16, /* FIS-based Switching Supported */
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PMD = 1 << 15, /* PIO Multiple DRQ Block */
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SSC = 1 << 14, /* Slumber State Capable */
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PSC = 1 << 13, /* Partial State Capable */
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CCCS = 1 << 7, /* Command Completion Coalescing Supported */
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EMS = 1 << 6, /* Enclosure Management Supported */
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SXS = 1 << 5 /* Supports External SATA */
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};
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enum HBACapabilitiesExtended : u32 {
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DESO = 1 << 5, /* DevSleep Entrance from Slumber Only */
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SADM = 1 << 4, /* Supports Aggressive Device Sleep Management */
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SDS = 1 << 3, /* Supports Device Sleep */
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APST = 1 << 2, /* Automatic Partial to Slumber Transitions */
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NVMP = 1 << 1, /* NVMHCI Present */
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BOH = 1 << 0, /* BIOS/OS Handoff */
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};
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// This structure is not defined by the AHCI spec, but is used within the code
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struct [[gnu::packed]] HBADefinedCapabilities {
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size_t ports_count { 1 };
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size_t max_command_list_entries_count { 1 };
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u8 interface_speed_generation { 1 };
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bool external_sata_supported : 1 { false };
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bool enclosure_management_supported : 1 { false };
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bool command_completion_coalescing_supported : 1 { false };
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bool partial_state_capable : 1 { false };
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bool slumber_state_capable : 1 { false };
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bool pio_multiple_drq_block : 1 { false };
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bool fis_based_switching_supported : 1 { false };
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bool port_multiplier_supported : 1 { false };
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bool ahci_mode_only : 1 { true };
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bool command_list_override_supported : 1 { false };
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bool activity_led_supported : 1 { false };
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bool aggressive_link_power_management_supported : 1 { false };
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bool staggered_spin_up_supported : 1 { false };
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bool mechanical_presence_switch_supported : 1 { false };
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bool snotification_register_supported : 1 { false };
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bool native_command_queuing_supported : 1 { false };
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bool addressing_64_bit_supported : 1 { false };
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bool bios_os_handoff : 1 { false };
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bool nvmhci_present : 1 { false };
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bool automatic_partial_to_slumber_transitions : 1 { false };
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bool device_sleep_supported : 1 { false };
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bool aggressive_device_sleep_management_supported : 1 { false };
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bool devsleep_entrance_from_slumber_only : 1 { false };
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};
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enum DeviceSignature : u32 {
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ATA = 0x00000101,
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ATAPI = 0xEB140101,
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EnclosureManagementBridge = 0xC33C0101,
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PortMultiplier = 0x96690101,
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Unconnected = 0xFFFFFFFF
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};
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enum class DeviceDetectionInitialization {
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NoActionRequested,
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PerformInterfaceInitializationSequence,
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DisableInterface
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};
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enum PortInterruptFlag : u32 {
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CPD = (u32)1 << 31, /* Cold Port Detect */
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TFE = 1 << 30, /* Task File Error */
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HBF = 1 << 29, /* Host Bus Fatal Error */
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HBD = 1 << 28, /* Host Bus Data Error */
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IF = 1 << 27, /* Interface Fatal Error */
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INF = 1 << 26, /* Interface Non-fatal Error */
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OF = 1 << 24, /* Overflow */
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IPM = 1 << 23, /* Incorrect Port Multiplier */
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PRC = 1 << 22, /* PhyRdy Change */
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DMP = 1 << 7, /* Device Mechanical Presence */
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PC = 1 << 6, /* Port Connect Change */
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DP = 1 << 5, /* Descriptor Processed */
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UF = 1 << 4, /* Unknown FIS */
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SDB = 1 << 3, /* Set Device FIS */
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DS = 1 << 2, /* DMA Setup FIS */
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PS = 1 << 1, /* PIO Setup FIS */
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DHR = 1 << 0 /* Device to Host Register FIS */
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};
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enum SErr : u32 {
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DIAG_X = 1 << 26, /* Exchanged */
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DIAG_F = 1 << 25, /* Unknown FIS Type */
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DIAG_T = 1 << 24, /* Transport state transition error */
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DIAG_S = 1 << 23, /* Link sequence error */
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DIAG_H = 1 << 22, /* Handshake error */
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DIAG_C = 1 << 21, /* CRC error */
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DIAG_D = 1 << 20, /* Disparity error */
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DIAG_B = 1 << 19, /* 10B to 8B decode error */
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DIAG_W = 1 << 18, /* Comm Wake */
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DIAG_I = 1 << 17, /* Phy Internal Error */
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DIAG_N = 1 << 16, /* PhyRdy Change */
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ERR_E = 1 << 11, /* Internal error */
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ERR_P = 1 << 10, /* Protocol error */
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ERR_C = 1 << 9, /* Persistent communication or data integrity error */
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ERR_T = 1 << 8, /* Transient data integrity error */
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ERR_M = 1 << 1, /* Received communications error */
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ERR_I = 1 << 0, /* Recovered data integrity error */
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};
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class PortInterruptStatusBitField {
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public:
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explicit PortInterruptStatusBitField(volatile u32& bitfield_register)
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: m_bitfield(bitfield_register)
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{
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}
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u32 raw_value() const { return m_bitfield; }
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bool is_set(PortInterruptFlag flag) const { return m_bitfield & (u32)flag; }
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void clear() { m_bitfield = 0xffffffff; }
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// Disable default implementations that would use surprising integer promotion.
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bool operator==(const MaskedBitField&) const = delete;
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bool operator<=(const MaskedBitField&) const = delete;
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bool operator>=(const MaskedBitField&) const = delete;
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bool operator<(const MaskedBitField&) const = delete;
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bool operator>(const MaskedBitField&) const = delete;
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private:
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volatile u32& m_bitfield;
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};
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class PortInterruptEnableBitField {
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public:
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explicit PortInterruptEnableBitField(volatile u32& bitfield_register)
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: m_bitfield(bitfield_register)
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{
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}
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u32 raw_value() const { return m_bitfield; }
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bool is_set(PortInterruptFlag flag) { return m_bitfield & (u32)flag; }
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void set_at(PortInterruptFlag flag) { m_bitfield = m_bitfield | static_cast<u32>(flag); }
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void clear() { m_bitfield = 0; }
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bool is_cleared() const { return m_bitfield == 0; }
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void set_all() { m_bitfield = 0xffffffff; }
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// Disable default implementations that would use surprising integer promotion.
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bool operator==(const MaskedBitField&) const = delete;
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bool operator<=(const MaskedBitField&) const = delete;
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bool operator>=(const MaskedBitField&) const = delete;
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bool operator<(const MaskedBitField&) const = delete;
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bool operator>(const MaskedBitField&) const = delete;
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private:
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volatile u32& m_bitfield;
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};
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struct [[gnu::packed]] PortRegisters {
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u32 clb; /* Port x Command List Base Address */
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u32 clbu; /* Port x Command List Base Address Upper 32-Bits */
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u32 fb; /* Port x FIS Base Address */
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u32 fbu; /* Port x FIS Base Address Upper 32-Bits */
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u32 is; /* Port x Interrupt Status */
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u32 ie; /* Port x Interrupt Enable */
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u32 cmd; /* Port x Command and Status */
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u32 reserved;
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u32 tfd; /* Port x Task File Data */
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u32 sig; /* Port x Signature */
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u32 ssts; /* Port x Serial ATA Status (SCR0: SStatus) */
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u32 sctl; /* Port x Serial ATA Control (SCR2: SControl) */
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u32 serr; /* Port x Serial ATA Error (SCR1: SError) */
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u32 sact; /* Port x Serial ATA Active (SCR3: SActive) */
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u32 ci; /* Port x Command Issue */
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u32 sntf; /* Port x Serial ATA Notification (SCR4: SNotification) */
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u32 fbs; /* Port x FIS-based Switching Control */
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u32 devslp; /* Port x Device Sleep */
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u8 reserved2[0x70 - 0x48];
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u8 vs[16]; /* Port x Vendor Specific */
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};
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struct [[gnu::packed]] GenericHostControl {
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u32 cap; /* Host Capabilities */
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u32 ghc; /* Global Host Control */
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u32 is; /* Interrupt Status */
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u32 pi; /* Ports Implemented */
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u32 version;
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u32 ccc_ctl; /* Command Completion Coalescing Control */
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u32 ccc_ports; /* Command Completion Coalsecing Ports */
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u32 em_loc; /* Enclosure Management Location */
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u32 em_ctl; /* Enclosure Management Control */
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u32 cap2; /* Host Capabilities Extended */
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u32 bohc; /* BIOS/OS Handoff Control and Status */
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};
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struct [[gnu::packed]] HBA {
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GenericHostControl control_regs;
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u8 reserved[52];
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u8 nvmhci[64];
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u8 vendor_specific[96];
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PortRegisters port_regs[32];
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};
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struct [[gnu::packed]] CommandHeader {
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u16 attributes;
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u16 prdtl; /* Physical Region Descriptor Table Length */
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u32 prdbc; /* Physical Region Descriptor Byte Count */
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u32 ctba; /* Command Table Descriptor Base Address */
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u32 ctbau; /* Command Table Descriptor Base Address Upper 32-bits */
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u32 reserved[4];
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};
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struct [[gnu::packed]] PhysicalRegionDescriptor {
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u32 base_low;
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u32 base_high;
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u32 reserved;
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u32 byte_count; /* Bit 31 - Interrupt completion, Bit 0 to 21 - Data Byte Count */
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};
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struct [[gnu::packed]] CommandTable {
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u8 command_fis[64];
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u8 atapi_command[32];
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u8 reserved[32];
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PhysicalRegionDescriptor descriptors[];
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};
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}
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