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When an exception is triggered on aarch64, the processor always switches to the exception stack which is defined by the SP_EL1 register.
97 lines
2.0 KiB
C++
97 lines
2.0 KiB
C++
/*
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* Copyright (c) 2021, James Mintram <me@jamesrm.com>
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* Copyright (c) 2021, Nico Weber <thakis@chromium.org>
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* Copyright (c) 2021, Marcin Undak <mcinek@gmail.com>
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* Copyright (c) 2021, Jesse Buhagiar <jooster669@gmail.com>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#pragma once
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#include <Kernel/Arch/aarch64/Registers.h>
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namespace Kernel::Aarch64::Asm {
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inline void set_ttbr1_el1(FlatPtr ttbr1_el1)
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{
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asm("msr ttbr1_el1, %[value]" ::[value] "r"(ttbr1_el1));
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}
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inline void set_ttbr0_el1(FlatPtr ttbr0_el1)
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{
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asm("msr ttbr0_el1, %[value]" ::[value] "r"(ttbr0_el1));
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}
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inline void set_sp_el1(FlatPtr sp_el1)
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{
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asm("msr sp_el1, %[value]" ::[value] "r"(sp_el1));
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}
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inline void flush()
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{
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asm("dsb ish");
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asm("isb");
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}
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[[noreturn]] inline void halt()
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{
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for (;;) {
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asm volatile("wfi");
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}
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}
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enum class ExceptionLevel : u8 {
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EL0 = 0,
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EL1 = 1,
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EL2 = 2,
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EL3 = 3,
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};
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inline ExceptionLevel get_current_exception_level()
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{
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u64 current_exception_level;
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asm("mrs %[value], CurrentEL"
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: [value] "=r"(current_exception_level));
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current_exception_level = (current_exception_level >> 2) & 0x3;
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return static_cast<ExceptionLevel>(current_exception_level);
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}
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inline void wait_cycles(int n)
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{
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// This is probably too fast when caching and branch prediction is turned on.
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// FIXME: Make timer-based.
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asm("mov x0, %[value]\n"
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"0:\n"
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" subs x0, x0, #1\n"
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" bne 0b" ::[value] "r"(n)
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: "x0");
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}
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inline void el1_vector_table_install(void* vector_table)
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{
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asm("msr VBAR_EL1, %[value]" ::[value] "r"(vector_table));
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}
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inline void enter_el2_from_el3()
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{
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asm volatile(" adr x0, entered_el2\n"
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" msr elr_el3, x0\n"
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" eret\n"
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"entered_el2:" ::
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: "x0");
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}
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inline void enter_el1_from_el2()
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{
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asm volatile(" adr x0, entered_el1\n"
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" msr elr_el2, x0\n"
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" eret\n"
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"entered_el1:" ::
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: "x0");
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}
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}
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