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8d9b6c57b5
We return the Optional container in find_redirection_entry_by_vector() method instead of a raw integer. This makes the code more readable and correct.
339 lines
12 KiB
C++
339 lines
12 KiB
C++
/*
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* Copyright (c) 2020, Liav A. <liavalb@hotmail.co.il>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <AK/Optional.h>
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#include <AK/StringView.h>
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#include <Kernel/ACPI/MultiProcessorParser.h>
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#include <Kernel/Arch/i386/CPU.h>
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#include <Kernel/Interrupts/APIC.h>
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#include <Kernel/Interrupts/IOAPIC.h>
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#include <Kernel/Interrupts/InterruptManagement.h>
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#include <Kernel/VM/MemoryManager.h>
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#define IOAPIC_REDIRECTION_ENTRY_OFFSET 0x10
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namespace Kernel {
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enum DeliveryMode {
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Normal = 0,
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LowPriority = 1,
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SMI = 2,
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NMI = 3,
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INIT = 4,
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External = 7
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};
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IOAPIC::IOAPIC(ioapic_mmio_regs& regs, u32 gsi_base)
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: m_physical_access_registers(regs)
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, m_gsi_base(gsi_base)
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, m_id((read_register(0x0) >> 24) & 0xFF)
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, m_version(read_register(0x1) & 0xFF)
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, m_redirection_entries_count((read_register(0x1) >> 16) + 1)
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{
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InterruptDisabler disabler;
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klog() << "IOAPIC ID: 0x" << String::format("%x", m_id);
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klog() << "IOAPIC Version: 0x" << String::format("%x", m_version) << ", Redirection Entries count - " << m_redirection_entries_count;
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klog() << "IOAPIC Arbitration ID 0x" << String::format("%x", read_register(0x2));
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mask_all_redirection_entries();
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}
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void IOAPIC::initialize()
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{
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}
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void IOAPIC::map_interrupt_redirection(u8 interrupt_vector)
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{
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InterruptDisabler disabler;
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for (auto redirection_override : InterruptManagement::the().isa_overrides()) {
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ASSERT(!redirection_override.is_null());
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if (redirection_override->source() != interrupt_vector)
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continue;
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bool active_low;
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// See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
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switch ((redirection_override->flags() & 0b11)) {
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case 0:
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active_low = false;
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break;
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case 1:
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active_low = false;
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break;
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case 2:
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ASSERT_NOT_REACHED(); // Reserved value
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case 3:
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active_low = true;
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break;
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}
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bool trigger_level_mode;
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// See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
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switch (((redirection_override->flags() >> 2) & 0b11)) {
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case 0:
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trigger_level_mode = false;
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break;
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case 1:
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trigger_level_mode = false;
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break;
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case 2:
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ASSERT_NOT_REACHED(); // Reserved value
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case 3:
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trigger_level_mode = true;
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break;
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}
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configure_redirection_entry(redirection_override->gsi() - gsi_base(), InterruptManagement::acquire_mapped_interrupt_number(redirection_override->source()) + IRQ_VECTOR_BASE, DeliveryMode::Normal, false, active_low, trigger_level_mode, true, 0);
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return;
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}
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isa_identity_map(interrupt_vector);
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}
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void IOAPIC::isa_identity_map(int index)
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{
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InterruptDisabler disabler;
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configure_redirection_entry(index, InterruptManagement::acquire_mapped_interrupt_number(index) + IRQ_VECTOR_BASE, DeliveryMode::Normal, false, false, false, true, 0);
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}
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void IOAPIC::map_pci_interrupts()
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{
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InterruptDisabler disabler;
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configure_redirection_entry(11, 11 + IRQ_VECTOR_BASE, DeliveryMode::Normal, false, false, true, true, 0);
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}
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bool IOAPIC::is_enabled() const
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{
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return !is_hard_disabled();
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}
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void IOAPIC::spurious_eoi(const GenericInterruptHandler& handler) const
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{
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InterruptDisabler disabler;
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ASSERT(handler.type() == HandlerType::SpuriousInterruptHandler);
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ASSERT(handler.interrupt_number() == APIC::spurious_interrupt_vector());
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klog() << "IOAPIC::spurious_eoi - Spurious Interrupt occurred";
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}
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void IOAPIC::map_isa_interrupts()
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{
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InterruptDisabler disabler;
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for (auto redirection_override : InterruptManagement::the().isa_overrides()) {
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ASSERT(!redirection_override.is_null());
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if ((redirection_override->gsi() < gsi_base()) || (redirection_override->gsi() >= (gsi_base() + m_redirection_entries_count)))
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continue;
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bool active_low;
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// See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
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switch ((redirection_override->flags() & 0b11)) {
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case 0:
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active_low = false;
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break;
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case 1:
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active_low = false;
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break;
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case 2:
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ASSERT_NOT_REACHED();
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case 3:
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active_low = true;
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break;
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}
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bool trigger_level_mode;
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// See ACPI spec Version 6.2, page 205 to learn more about Interrupt Overriding Flags.
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switch (((redirection_override->flags() >> 2) & 0b11)) {
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case 0:
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trigger_level_mode = false;
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break;
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case 1:
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trigger_level_mode = false;
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break;
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case 2:
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ASSERT_NOT_REACHED();
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case 3:
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trigger_level_mode = true;
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break;
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}
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configure_redirection_entry(redirection_override->gsi() - gsi_base(), InterruptManagement::acquire_mapped_interrupt_number(redirection_override->source()) + IRQ_VECTOR_BASE, 0, false, active_low, trigger_level_mode, true, 0);
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}
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}
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void IOAPIC::reset_all_redirection_entries() const
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{
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InterruptDisabler disabler;
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for (size_t index = 0; index < m_redirection_entries_count; index++)
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reset_redirection_entry(index);
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}
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void IOAPIC::hard_disable()
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{
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InterruptDisabler disabler;
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reset_all_redirection_entries();
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IRQController::hard_disable();
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}
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void IOAPIC::reset_redirection_entry(int index) const
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{
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InterruptDisabler disabler;
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configure_redirection_entry(index, 0, 0, false, false, false, true, 0);
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}
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void IOAPIC::configure_redirection_entry(int index, u8 interrupt_vector, u8 delivery_mode, bool logical_destination, bool active_low, bool trigger_level_mode, bool masked, u8 destination) const
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{
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InterruptDisabler disabler;
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ASSERT((u32)index < m_redirection_entries_count);
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u32 redirection_entry1 = interrupt_vector | (delivery_mode & 0b111) << 8 | logical_destination << 11 | active_low << 13 | trigger_level_mode << 15 | masked << 16;
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u32 redirection_entry2 = destination << 24;
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write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry1);
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#ifdef IOAPIC_DEBUG
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dbg() << "IOAPIC Value: 0x" << String::format("%x", read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET));
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#endif
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write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET + 1, redirection_entry2);
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#ifdef IOAPIC_DEBUG
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dbg() << "IOAPIC Value: 0x" << String::format("%x", read_register((index << 1) + 0x11));
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#endif
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}
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void IOAPIC::mask_all_redirection_entries() const
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{
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InterruptDisabler disabler;
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for (size_t index = 0; index < m_redirection_entries_count; index++)
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mask_redirection_entry(index);
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}
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void IOAPIC::mask_redirection_entry(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET);
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if (redirection_entry & (1 << 16))
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return;
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write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry | (1 << 16));
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}
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bool IOAPIC::is_redirection_entry_masked(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & (1 << 16)) != 0;
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}
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void IOAPIC::unmask_redirection_entry(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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u32 redirection_entry = read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET);
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if (!(redirection_entry & (1 << 16)))
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return;
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write_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET, redirection_entry & ~(1 << 16));
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}
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bool IOAPIC::is_vector_enabled(u8 interrupt_vector) const
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{
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InterruptDisabler disabler;
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return is_redirection_entry_masked(interrupt_vector);
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}
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u8 IOAPIC::read_redirection_entry_vector(u8 index) const
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{
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ASSERT((u32)index < m_redirection_entries_count);
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return (read_register((index << 1) + IOAPIC_REDIRECTION_ENTRY_OFFSET) & 0xFF);
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}
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Optional<int> IOAPIC::find_redirection_entry_by_vector(u8 vector) const
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{
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InterruptDisabler disabler;
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for (size_t index = 0; index < m_redirection_entries_count; index++) {
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if (read_redirection_entry_vector(index) == (InterruptManagement::acquire_mapped_interrupt_number(vector) + IRQ_VECTOR_BASE))
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return index;
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}
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return {};
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}
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void IOAPIC::disable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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u8 interrupt_vector = handler.interrupt_number();
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ASSERT(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
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auto found_index = find_redirection_entry_by_vector(interrupt_vector);
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if (!found_index.has_value()) {
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map_interrupt_redirection(interrupt_vector);
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found_index = find_redirection_entry_by_vector(interrupt_vector);
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}
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ASSERT(found_index.has_value());
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mask_redirection_entry(found_index.value());
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}
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void IOAPIC::enable(const GenericInterruptHandler& handler)
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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u8 interrupt_vector = handler.interrupt_number();
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ASSERT(interrupt_vector >= gsi_base() && interrupt_vector < interrupt_vectors_count());
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auto found_index = find_redirection_entry_by_vector(interrupt_vector);
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if (!found_index.has_value()) {
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map_interrupt_redirection(interrupt_vector);
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found_index = find_redirection_entry_by_vector(interrupt_vector);
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}
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ASSERT(found_index.has_value());
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unmask_redirection_entry(found_index.value());
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}
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void IOAPIC::eoi(const GenericInterruptHandler& handler) const
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{
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InterruptDisabler disabler;
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ASSERT(!is_hard_disabled());
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ASSERT(handler.interrupt_number() >= gsi_base() && handler.interrupt_number() < interrupt_vectors_count());
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ASSERT(handler.type() != HandlerType::SpuriousInterruptHandler);
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APIC::eoi();
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}
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u16 IOAPIC::get_isr() const
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{
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InterruptDisabler disabler;
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ASSERT_NOT_REACHED();
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}
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u16 IOAPIC::get_irr() const
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{
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InterruptDisabler disabler;
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ASSERT_NOT_REACHED();
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}
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void IOAPIC::write_register(u32 index, u32 value) const
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{
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InterruptDisabler disabler;
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auto region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(&m_physical_access_registers)), (PAGE_SIZE * 2), "IOAPIC Write", Region::Access::Read | Region::Access::Write);
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auto& regs = *(volatile ioapic_mmio_regs*)region->vaddr().offset(offset_in_page(&m_physical_access_registers)).as_ptr();
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regs.select = index;
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regs.window = value;
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#ifdef IOAPIC_DEBUG
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dbg() << "IOAPIC Writing, Value 0x" << String::format("%x", regs.window) << " @ offset 0x" << String::format("%x", regs.select);
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#endif
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}
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u32 IOAPIC::read_register(u32 index) const
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{
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InterruptDisabler disabler;
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auto region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(&m_physical_access_registers)), (PAGE_SIZE * 2), "IOAPIC Read", Region::Access::Read | Region::Access::Write);
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auto& regs = *(volatile ioapic_mmio_regs*)region->vaddr().offset(offset_in_page(&m_physical_access_registers)).as_ptr();
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regs.select = index;
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#ifdef IOAPIC_DEBUG
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dbg() << "IOAPIC Reading, Value 0x" << String::format("%x", regs.window) << " @ offset 0x" << String::format("%x", regs.select);
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#endif
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return regs.window;
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}
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}
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