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25ea7461a0
A couple of things were changed: 1. Semantic changes - PCI segments are now called PCI domains, to better match what they are really. It's also the name that Linux gave, and it seems that Wikipedia also uses this name. We also remove PCI::ChangeableAddress, because it was used in the past but now it's no longer being used. 2. There are no WindowedMMIOAccess or MMIOAccess classes anymore, as they made a bunch of unnecessary complexity. Instead, Windowed access is removed entirely (this was tested, but never was benchmarked), so we are left with IO access and memory access options. The memory access option is essentially mapping the PCI bus (from the chosen PCI domain), to virtual memory as-is. This means that unless needed, at any time, there is only one PCI bus being mapped, and this is changed if access to another PCI bus in the same PCI domain is needed. For now, we don't support mapping of different PCI buses from different PCI domains at the same time, because basically it's still a non-issue for most machines out there. 2. OOM-safety is increased, especially when constructing the Access object. It means that we pre-allocating any needed resources, and we try to find PCI domains (if requested to initialize memory access) after we attempt to construct the Access object, so it's possible to fail at this point "gracefully". 3. All PCI API functions are now separated into a different header file, which means only "clients" of the PCI subsystem API will need to include that header file. 4. Functional changes - we only allow now to enumerate the bus after a hardware scan. This means that the old method "enumerate_hardware" is removed, so, when initializing an Access object, the initializing function must call rescan on it to force it to find devices. This makes it possible to fail rescan, and also to defer it after construction from both OOM-safety terms and hotplug capabilities.
201 lines
6.6 KiB
C++
201 lines
6.6 KiB
C++
/*
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* Copyright (c) 2021, Liav A. <liavalb@hotmail.co.il>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <AK/Atomic.h>
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#include <AK/OwnPtr.h>
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#include <AK/RefPtr.h>
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#include <AK/Types.h>
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#include <Kernel/Bus/PCI/API.h>
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#include <Kernel/Memory/MemoryManager.h>
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#include <Kernel/Storage/AHCIController.h>
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#include <Kernel/Storage/SATADiskDevice.h>
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namespace Kernel {
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NonnullRefPtr<AHCIController> AHCIController::initialize(PCI::Address address)
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{
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return adopt_ref(*new AHCIController(address));
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}
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bool AHCIController::reset()
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{
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hba().control_regs.ghc = 1;
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dbgln_if(AHCI_DEBUG, "{}: AHCI Controller reset", pci_address());
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full_memory_barrier();
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size_t retry = 0;
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while (true) {
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if (retry > 1000)
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return false;
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if (!(hba().control_regs.ghc & 1))
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break;
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IO::delay(1000);
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retry++;
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}
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// The HBA is locked or hung if we waited more than 1 second!
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return true;
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}
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bool AHCIController::shutdown()
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{
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TODO();
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}
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size_t AHCIController::devices_count() const
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{
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size_t count = 0;
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for (auto& port_handler : m_handlers) {
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port_handler.enumerate_ports([&](const AHCIPort& port) {
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if (port.connected_device())
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count++;
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});
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}
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return count;
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}
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void AHCIController::start_request(const StorageDevice&, AsyncBlockDeviceRequest&)
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{
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VERIFY_NOT_REACHED();
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}
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void AHCIController::complete_current_request(AsyncDeviceRequest::RequestResult)
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{
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VERIFY_NOT_REACHED();
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}
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volatile AHCI::PortRegisters& AHCIController::port(size_t port_number) const
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{
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VERIFY(port_number < (size_t)AHCI::Limits::MaxPorts);
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return static_cast<volatile AHCI::PortRegisters&>(hba().port_regs[port_number]);
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}
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volatile AHCI::HBA& AHCIController::hba() const
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{
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return static_cast<volatile AHCI::HBA&>(*(volatile AHCI::HBA*)(m_hba_region->vaddr().as_ptr()));
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}
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AHCIController::AHCIController(PCI::Address address)
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: StorageController()
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, PCI::Device(address)
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, m_hba_region(default_hba_region())
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, m_capabilities(capabilities())
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{
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initialize();
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}
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AHCI::HBADefinedCapabilities AHCIController::capabilities() const
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{
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u32 capabilities = hba().control_regs.cap;
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u32 extended_capabilities = hba().control_regs.cap2;
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dbgln_if(AHCI_DEBUG, "{}: AHCI Controller Capabilities = {:#08x}, Extended Capabilities = {:#08x}", pci_address(), capabilities, extended_capabilities);
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return (AHCI::HBADefinedCapabilities) {
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(capabilities & 0b11111) + 1,
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((capabilities >> 8) & 0b11111) + 1,
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(u8)((capabilities >> 20) & 0b1111),
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(capabilities & (u32)(AHCI::HBACapabilities::SXS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::EMS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::CCCS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::PSC)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SSC)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::PMD)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::FBSS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SPM)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SAM)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SCLO)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SAL)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SALP)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SSS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SMPS)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SSNTF)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::SNCQ)) != 0,
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(capabilities & (u32)(AHCI::HBACapabilities::S64A)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::BOH)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::NVMP)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::APST)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::SDS)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::SADM)) != 0,
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(extended_capabilities & (u32)(AHCI::HBACapabilitiesExtended::DESO)) != 0
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};
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}
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NonnullOwnPtr<Memory::Region> AHCIController::default_hba_region() const
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{
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return MM.allocate_kernel_region(PhysicalAddress(PCI::get_BAR5(pci_address())).page_base(), Memory::page_round_up(sizeof(AHCI::HBA)), "AHCI HBA", Memory::Region::Access::ReadWrite).release_value();
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}
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AHCIController::~AHCIController()
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{
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}
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void AHCIController::initialize()
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{
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if (!reset()) {
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dmesgln("{}: AHCI controller reset failed", pci_address());
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return;
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}
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dmesgln("{}: AHCI controller reset", pci_address());
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dbgln("{}: AHCI command list entries count - {}", pci_address(), hba_capabilities().max_command_list_entries_count);
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u32 version = hba().control_regs.version;
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dbgln_if(AHCI_DEBUG, "{}: AHCI Controller Version = {:#08x}", pci_address(), version);
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hba().control_regs.ghc = 0x80000000; // Ensure that HBA knows we are AHCI aware.
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PCI::enable_interrupt_line(pci_address());
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PCI::enable_bus_mastering(pci_address());
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enable_global_interrupts();
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m_handlers.append(AHCIPortHandler::create(*this, PCI::get_interrupt_line(pci_address()),
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AHCI::MaskedBitField((volatile u32&)(hba().control_regs.pi))));
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}
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void AHCIController::disable_global_interrupts() const
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{
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hba().control_regs.ghc = hba().control_regs.ghc & 0xfffffffd;
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}
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void AHCIController::enable_global_interrupts() const
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{
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hba().control_regs.ghc = hba().control_regs.ghc | (1 << 1);
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}
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RefPtr<StorageDevice> AHCIController::device_by_port(u32 port_index) const
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{
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for (auto& port_handler : m_handlers) {
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if (!port_handler.is_responsible_for_port_index(port_index))
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continue;
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auto port = port_handler.port_at_index(port_index);
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if (!port)
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return nullptr;
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return port->connected_device();
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}
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return nullptr;
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}
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RefPtr<StorageDevice> AHCIController::device(u32 index) const
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{
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NonnullRefPtrVector<StorageDevice> connected_devices;
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u32 pi = hba().control_regs.pi;
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u32 bit = __builtin_ffsl(pi);
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while (bit) {
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dbgln_if(AHCI_DEBUG, "Checking implemented port {}, pi {:b}", bit - 1, pi);
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pi &= ~(1u << (bit - 1));
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auto checked_device = device_by_port(bit - 1);
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bit = __builtin_ffsl(pi);
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if (checked_device.is_null())
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continue;
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connected_devices.append(checked_device.release_nonnull());
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}
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dbgln_if(AHCI_DEBUG, "Connected device count: {}, Index: {}", connected_devices.size(), index);
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if (index >= connected_devices.size())
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return nullptr;
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return connected_devices[index];
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}
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}
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