mirror of
https://github.com/LadybirdBrowser/ladybird.git
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06e7fc9dee
This is not a complete fix, since spurious IRQs under heavy loads can still occur. However, this fix limits the amount of spurious IRQs. It is encouraged to provide a better fix in the future, probably something that takes into account handling of PCI level-triggered interrupts.
440 lines
15 KiB
C++
440 lines
15 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <Kernel/Net/E1000NetworkAdapter.h>
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#include <Kernel/Thread.h>
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#include <LibBareMetal/IO.h>
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//#define E1000_DEBUG
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namespace Kernel {
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#define REG_CTRL 0x0000
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#define REG_STATUS 0x0008
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#define REG_EEPROM 0x0014
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#define REG_CTRL_EXT 0x0018
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#define REG_INTERRUPT_CAUSE_READ 0x00C0
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#define REG_INTERRUPT_RATE 0x00C4
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#define REG_INTERRUPT_MASK_SET 0x00D0
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#define REG_INTERRUPT_MASK_CLEAR 0x00D8
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#define REG_RCTRL 0x0100
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#define REG_RXDESCLO 0x2800
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#define REG_RXDESCHI 0x2804
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#define REG_RXDESCLEN 0x2808
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#define REG_RXDESCHEAD 0x2810
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#define REG_RXDESCTAIL 0x2818
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#define REG_TCTRL 0x0400
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#define REG_TXDESCLO 0x3800
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#define REG_TXDESCHI 0x3804
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#define REG_TXDESCLEN 0x3808
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#define REG_TXDESCHEAD 0x3810
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#define REG_TXDESCTAIL 0x3818
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#define REG_RDTR 0x2820 // RX Delay Timer Register
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#define REG_RXDCTL 0x3828 // RX Descriptor Control
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#define REG_RADV 0x282C // RX Int. Absolute Delay Timer
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#define REG_RSRPD 0x2C00 // RX Small Packet Detect Interrupt
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#define REG_TIPG 0x0410 // Transmit Inter Packet Gap
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#define ECTRL_SLU 0x40 //set link up
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#define RCTL_EN (1 << 1) // Receiver Enable
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#define RCTL_SBP (1 << 2) // Store Bad Packets
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#define RCTL_UPE (1 << 3) // Unicast Promiscuous Enabled
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#define RCTL_MPE (1 << 4) // Multicast Promiscuous Enabled
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#define RCTL_LPE (1 << 5) // Long Packet Reception Enable
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#define RCTL_LBM_NONE (0 << 6) // No Loopback
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#define RCTL_LBM_PHY (3 << 6) // PHY or external SerDesc loopback
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#define RTCL_RDMTS_HALF (0 << 8) // Free Buffer Threshold is 1/2 of RDLEN
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#define RTCL_RDMTS_QUARTER (1 << 8) // Free Buffer Threshold is 1/4 of RDLEN
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#define RTCL_RDMTS_EIGHTH (2 << 8) // Free Buffer Threshold is 1/8 of RDLEN
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#define RCTL_MO_36 (0 << 12) // Multicast Offset - bits 47:36
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#define RCTL_MO_35 (1 << 12) // Multicast Offset - bits 46:35
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#define RCTL_MO_34 (2 << 12) // Multicast Offset - bits 45:34
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#define RCTL_MO_32 (3 << 12) // Multicast Offset - bits 43:32
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#define RCTL_BAM (1 << 15) // Broadcast Accept Mode
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#define RCTL_VFE (1 << 18) // VLAN Filter Enable
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#define RCTL_CFIEN (1 << 19) // Canonical Form Indicator Enable
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#define RCTL_CFI (1 << 20) // Canonical Form Indicator Bit Value
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#define RCTL_DPF (1 << 22) // Discard Pause Frames
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#define RCTL_PMCF (1 << 23) // Pass MAC Control Frames
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#define RCTL_SECRC (1 << 26) // Strip Ethernet CRC
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// Buffer Sizes
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#define RCTL_BSIZE_256 (3 << 16)
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#define RCTL_BSIZE_512 (2 << 16)
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#define RCTL_BSIZE_1024 (1 << 16)
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#define RCTL_BSIZE_2048 (0 << 16)
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#define RCTL_BSIZE_4096 ((3 << 16) | (1 << 25))
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#define RCTL_BSIZE_8192 ((2 << 16) | (1 << 25))
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#define RCTL_BSIZE_16384 ((1 << 16) | (1 << 25))
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// Transmit Command
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#define CMD_EOP (1 << 0) // End of Packet
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#define CMD_IFCS (1 << 1) // Insert FCS
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#define CMD_IC (1 << 2) // Insert Checksum
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#define CMD_RS (1 << 3) // Report Status
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#define CMD_RPS (1 << 4) // Report Packet Sent
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#define CMD_VLE (1 << 6) // VLAN Packet Enable
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#define CMD_IDE (1 << 7) // Interrupt Delay Enable
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// TCTL Register
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#define TCTL_EN (1 << 1) // Transmit Enable
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#define TCTL_PSP (1 << 3) // Pad Short Packets
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#define TCTL_CT_SHIFT 4 // Collision Threshold
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#define TCTL_COLD_SHIFT 12 // Collision Distance
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#define TCTL_SWXOFF (1 << 22) // Software XOFF Transmission
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#define TCTL_RTLC (1 << 24) // Re-transmit on Late Collision
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#define TSTA_DD (1 << 0) // Descriptor Done
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#define TSTA_EC (1 << 1) // Excess Collisions
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#define TSTA_LC (1 << 2) // Late Collision
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#define LSTA_TU (1 << 3) // Transmit Underrun
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// STATUS Register
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#define STATUS_FD 0x01
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#define STATUS_LU 0x02
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#define STATUS_TXOFF 0x08
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#define STATUS_SPEED 0xC0
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#define STATUS_SPEED_10MB 0x00
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#define STATUS_SPEED_100MB 0x40
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#define STATUS_SPEED_1000MB1 0x80
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#define STATUS_SPEED_1000MB2 0xC0
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// Interrupt Masks
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#define INTERRUPT_TXDW (1 << 0)
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#define INTERRUPT_TXQE (1 << 1)
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#define INTERRUPT_LSC (1 << 2)
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#define INTERRUPT_RXSEQ (1 << 3)
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#define INTERRUPT_RXDMT0 (1 << 4)
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#define INTERRUPT_RXO (1 << 6)
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#define INTERRUPT_RXT0 (1 << 7)
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#define INTERRUPT_MDAC (1 << 9)
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#define INTERRUPT_RXCFG (1 << 10)
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#define INTERRUPT_PHYINT (1 << 12)
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#define INTERRUPT_TXD_LOW (1 << 15)
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#define INTERRUPT_SRPD (1 << 16)
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void E1000NetworkAdapter::detect(const PCI::Address& address)
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{
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if (address.is_null())
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return;
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static const PCI::ID qemu_bochs_vbox_id = { 0x8086, 0x100e };
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const PCI::ID id = PCI::get_id(address);
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if (id != qemu_bochs_vbox_id)
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return;
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u8 irq = PCI::get_interrupt_line(address);
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(void)adopt(*new E1000NetworkAdapter(address, irq)).leak_ref();
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}
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E1000NetworkAdapter::E1000NetworkAdapter(PCI::Address address, u8 irq)
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: PCI::Device(address, irq)
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, m_io_base(PCI::get_BAR1(pci_address()) & ~1)
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, m_rx_descriptors_region(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(sizeof(e1000_rx_desc) * number_of_rx_descriptors + 16), "E1000 RX", Region::Access::Read | Region::Access::Write))
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, m_tx_descriptors_region(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(sizeof(e1000_tx_desc) * number_of_tx_descriptors + 16), "E1000 TX", Region::Access::Read | Region::Access::Write))
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{
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set_interface_name("e1k");
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klog() << "E1000: Found @ " << pci_address();
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enable_bus_mastering(pci_address());
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size_t mmio_base_size = PCI::get_BAR_Space_Size(pci_address(), 0);
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m_mmio_region = MM.allocate_kernel_region(PhysicalAddress(page_base_of(PCI::get_BAR0(pci_address()))), PAGE_ROUND_UP(mmio_base_size), "E1000 MMIO", Region::Access::Read | Region::Access::Write, false, false);
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m_mmio_base = m_mmio_region->vaddr();
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m_use_mmio = true;
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m_interrupt_line = PCI::get_interrupt_line(pci_address());
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klog() << "E1000: port base: " << m_io_base;
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klog() << "E1000: MMIO base: " << PhysicalAddress(PCI::get_BAR0(pci_address()) & 0xfffffffc);
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klog() << "E1000: MMIO base size: " << mmio_base_size << " bytes";
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klog() << "E1000: Interrupt line: " << m_interrupt_line;
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detect_eeprom();
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klog() << "E1000: Has EEPROM? " << m_has_eeprom;
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read_mac_address();
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const auto& mac = mac_address();
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klog() << "E1000: MAC address: " << String::format("%b", mac[0]) << ":" << String::format("%b", mac[1]) << ":" << String::format("%b", mac[2]) << ":" << String::format("%b", mac[3]) << ":" << String::format("%b", mac[4]) << ":" << String::format("%b", mac[5]);
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u32 flags = in32(REG_CTRL);
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out32(REG_CTRL, flags | ECTRL_SLU);
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out16(REG_INTERRUPT_RATE, 6000); // Interrupt rate of 1.536 milliseconds
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initialize_rx_descriptors();
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initialize_tx_descriptors();
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out32(REG_INTERRUPT_MASK_SET, 0x1f6dc);
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out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0);
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in32(REG_INTERRUPT_CAUSE_READ);
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enable_irq();
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}
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E1000NetworkAdapter::~E1000NetworkAdapter()
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{
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}
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void E1000NetworkAdapter::handle_irq(const RegisterState&)
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{
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out32(REG_INTERRUPT_MASK_CLEAR, 0xffffffff);
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u32 status = in32(REG_INTERRUPT_CAUSE_READ);
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if (status & 4) {
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u32 flags = in32(REG_CTRL);
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out32(REG_CTRL, flags | ECTRL_SLU);
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}
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if (status & 0x80) {
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receive();
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}
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if (status & 0x10) {
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// Threshold OK?
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}
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m_wait_queue.wake_all();
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out32(REG_INTERRUPT_MASK_SET, INTERRUPT_LSC | INTERRUPT_RXT0 | INTERRUPT_RXO);
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}
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void E1000NetworkAdapter::detect_eeprom()
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{
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out32(REG_EEPROM, 0x1);
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for (volatile int i = 0; i < 999; ++i) {
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u32 data = in32(REG_EEPROM);
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if (data & 0x10) {
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m_has_eeprom = true;
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return;
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}
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}
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m_has_eeprom = false;
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}
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u32 E1000NetworkAdapter::read_eeprom(u8 address)
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{
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u16 data = 0;
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u32 tmp = 0;
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if (m_has_eeprom) {
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out32(REG_EEPROM, ((u32)address << 8) | 1);
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while (!((tmp = in32(REG_EEPROM)) & (1 << 4)))
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;
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} else {
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out32(REG_EEPROM, ((u32)address << 2) | 1);
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while (!((tmp = in32(REG_EEPROM)) & (1 << 1)))
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;
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}
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data = (tmp >> 16) & 0xffff;
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return data;
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}
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void E1000NetworkAdapter::read_mac_address()
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{
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if (m_has_eeprom) {
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u8 mac[6];
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u32 tmp = read_eeprom(0);
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mac[0] = tmp & 0xff;
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mac[1] = tmp >> 8;
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tmp = read_eeprom(1);
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mac[2] = tmp & 0xff;
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mac[3] = tmp >> 8;
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tmp = read_eeprom(2);
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mac[4] = tmp & 0xff;
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mac[5] = tmp >> 8;
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set_mac_address(mac);
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} else {
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ASSERT_NOT_REACHED();
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}
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}
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bool E1000NetworkAdapter::link_up()
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{
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return (in32(REG_STATUS) & STATUS_LU);
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}
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void E1000NetworkAdapter::initialize_rx_descriptors()
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{
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auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
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for (int i = 0; i < number_of_rx_descriptors; ++i) {
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auto& descriptor = rx_descriptors[i];
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m_rx_buffers_regions.append(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(8192), "E1000 RX buffer", Region::Access::Read | Region::Access::Write));
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descriptor.addr = m_rx_buffers_regions[i]->vmobject().physical_pages()[0]->paddr().get();
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descriptor.status = 0;
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}
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out32(REG_RXDESCLO, m_rx_descriptors_region->vmobject().physical_pages()[0]->paddr().get());
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out32(REG_RXDESCHI, 0);
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out32(REG_RXDESCLEN, number_of_rx_descriptors * sizeof(e1000_rx_desc));
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out32(REG_RXDESCHEAD, 0);
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out32(REG_RXDESCTAIL, number_of_rx_descriptors - 1);
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out32(REG_RCTRL, RCTL_EN | RCTL_SBP | RCTL_UPE | RCTL_MPE | RCTL_LBM_NONE | RTCL_RDMTS_HALF | RCTL_BAM | RCTL_SECRC | RCTL_BSIZE_8192);
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}
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void E1000NetworkAdapter::initialize_tx_descriptors()
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{
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auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
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for (int i = 0; i < number_of_tx_descriptors; ++i) {
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auto& descriptor = tx_descriptors[i];
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m_tx_buffers_regions.append(MM.allocate_contiguous_kernel_region(PAGE_ROUND_UP(8192), "E1000 TX buffer", Region::Access::Read | Region::Access::Write));
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descriptor.addr = m_tx_buffers_regions[i]->vmobject().physical_pages()[0]->paddr().get();
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descriptor.cmd = 0;
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}
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out32(REG_TXDESCLO, m_tx_descriptors_region->vmobject().physical_pages()[0]->paddr().get());
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out32(REG_TXDESCHI, 0);
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out32(REG_TXDESCLEN, number_of_tx_descriptors * sizeof(e1000_tx_desc));
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out32(REG_TXDESCHEAD, 0);
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out32(REG_TXDESCTAIL, 0);
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out32(REG_TCTRL, in32(REG_TCTRL) | TCTL_EN | TCTL_PSP);
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out32(REG_TIPG, 0x0060200A);
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}
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void E1000NetworkAdapter::out8(u16 address, u8 data)
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{
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#ifdef E1000_DEBUG
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dbg() << "E1000: OUT @ 0x" << address;
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#endif
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if (m_use_mmio) {
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auto* ptr = (volatile u8*)(m_mmio_base.get() + address);
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*ptr = data;
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return;
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}
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m_io_base.offset(address).out(data);
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}
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void E1000NetworkAdapter::out16(u16 address, u16 data)
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{
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#ifdef E1000_DEBUG
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dbg() << "E1000: OUT @ 0x" << address;
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#endif
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if (m_use_mmio) {
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auto* ptr = (volatile u16*)(m_mmio_base.get() + address);
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*ptr = data;
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return;
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}
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m_io_base.offset(address).out(data);
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}
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void E1000NetworkAdapter::out32(u16 address, u32 data)
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{
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#ifdef E1000_DEBUG
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dbg() << "E1000: OUT @ 0x" << address;
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#endif
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if (m_use_mmio) {
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auto* ptr = (volatile u32*)(m_mmio_base.get() + address);
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*ptr = data;
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return;
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}
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m_io_base.offset(address).out(data);
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}
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u8 E1000NetworkAdapter::in8(u16 address)
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{
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#ifdef E1000_DEBUG
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dbg() << "E1000: IN @ 0x" << address;
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#endif
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if (m_use_mmio)
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return *(volatile u8*)(m_mmio_base.get() + address);
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return m_io_base.offset(address).in<u8>();
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}
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u16 E1000NetworkAdapter::in16(u16 address)
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{
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#ifdef E1000_DEBUG
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dbg() << "E1000: IN @ 0x " << address;
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#endif
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if (m_use_mmio)
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return *(volatile u16*)(m_mmio_base.get() + address);
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return m_io_base.offset(address).in<u16>();
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}
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u32 E1000NetworkAdapter::in32(u16 address)
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{
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#ifdef E1000_DEBUG
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dbg() << "E1000: IN @ 0x" << address;
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#endif
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if (m_use_mmio)
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return *(volatile u32*)(m_mmio_base.get() + address);
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return m_io_base.offset(address).in<u32>();
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}
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void E1000NetworkAdapter::send_raw(const u8* data, size_t length)
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{
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disable_irq();
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u32 tx_current = in32(REG_TXDESCTAIL);
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#ifdef E1000_DEBUG
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klog() << "E1000: Sending packet (" << length << " bytes)";
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#endif
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auto* tx_descriptors = (e1000_tx_desc*)m_tx_descriptors_region->vaddr().as_ptr();
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auto& descriptor = tx_descriptors[tx_current];
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ASSERT(length <= 8192);
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auto* vptr = (void*)m_tx_buffers_regions[tx_current]->vaddr().as_ptr();
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memcpy(vptr, data, length);
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descriptor.length = length;
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descriptor.status = 0;
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descriptor.cmd = CMD_EOP | CMD_IFCS | CMD_RS;
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#ifdef E1000_DEBUG
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klog() << "E1000: Using tx descriptor " << tx_current << " (head is at " << in32(REG_TXDESCHEAD) << ")";
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#endif
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tx_current = (tx_current + 1) % number_of_tx_descriptors;
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cli();
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enable_irq();
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out32(REG_TXDESCTAIL, tx_current);
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for (;;) {
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if (descriptor.status) {
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sti();
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break;
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}
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Thread::current->wait_on(m_wait_queue);
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}
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#ifdef E1000_DEBUG
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klog() << "E1000: Sent packet, status is now " << String::format("%b", descriptor.status) << "!";
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#endif
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}
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void E1000NetworkAdapter::receive()
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{
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auto* rx_descriptors = (e1000_tx_desc*)m_rx_descriptors_region->vaddr().as_ptr();
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u32 rx_current;
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for (;;) {
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rx_current = in32(REG_RXDESCTAIL);
|
|
if (rx_current == in32(REG_RXDESCHEAD))
|
|
return;
|
|
rx_current = (rx_current + 1) % number_of_rx_descriptors;
|
|
if (!(rx_descriptors[rx_current].status & 1))
|
|
break;
|
|
auto* buffer = m_rx_buffers_regions[rx_current]->vaddr().as_ptr();
|
|
u16 length = rx_descriptors[rx_current].length;
|
|
#ifdef E1000_DEBUG
|
|
klog() << "E1000: Received 1 packet @ " << buffer << " (" << length << ") bytes!";
|
|
#endif
|
|
did_receive(buffer, length);
|
|
rx_descriptors[rx_current].status = 0;
|
|
out32(REG_RXDESCTAIL, rx_current);
|
|
}
|
|
}
|
|
|
|
}
|