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f4cec2f110
Also tweak the kernel's Makefile to use -nostdinc and -nostdinc++. This prevents us from picking up random headers from ../Root, which may include older versions of kernel headers. Since we still need <initializer_list> for Vector, we specifically include the necessary GCC path. This is a bit hackish but it works for now.
530 lines
14 KiB
C++
530 lines
14 KiB
C++
#include <Kernel/Devices/IDEDiskDevice.h>
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#include <Kernel/FileSystem/ProcFS.h>
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#include <Kernel/IO.h>
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#include <Kernel/Arch/i386/PIC.h>
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#include <Kernel/Process.h>
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#include <Kernel/StdLib.h>
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#include <Kernel/VM/MemoryManager.h>
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//#define DISK_DEBUG
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#define IRQ_FIXED_DISK 14
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#define ATA_SR_BSY 0x80
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#define ATA_SR_DRDY 0x40
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#define ATA_SR_DF 0x20
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#define ATA_SR_DSC 0x10
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#define ATA_SR_DRQ 0x08
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#define ATA_SR_CORR 0x04
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#define ATA_SR_IDX 0x02
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#define ATA_SR_ERR 0x01
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#define ATA_ER_BBK 0x80
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#define ATA_ER_UNC 0x40
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#define ATA_ER_MC 0x20
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#define ATA_ER_IDNF 0x10
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#define ATA_ER_MCR 0x08
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#define ATA_ER_ABRT 0x04
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#define ATA_ER_TK0NF 0x02
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#define ATA_ER_AMNF 0x01
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#define ATA_CMD_READ_PIO 0x20
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#define ATA_CMD_READ_PIO_EXT 0x24
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#define ATA_CMD_READ_DMA 0xC8
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#define ATA_CMD_READ_DMA_EXT 0x25
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#define ATA_CMD_WRITE_PIO 0x30
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#define ATA_CMD_WRITE_PIO_EXT 0x34
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#define ATA_CMD_WRITE_DMA 0xCA
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#define ATA_CMD_WRITE_DMA_EXT 0x35
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#define ATA_CMD_CACHE_FLUSH 0xE7
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#define ATA_CMD_CACHE_FLUSH_EXT 0xEA
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#define ATA_CMD_PACKET 0xA0
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#define ATA_CMD_IDENTIFY_PACKET 0xA1
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#define ATA_CMD_IDENTIFY 0xEC
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#define ATAPI_CMD_READ 0xA8
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#define ATAPI_CMD_EJECT 0x1B
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#define ATA_IDENT_DEVICETYPE 0
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#define ATA_IDENT_CYLINDERS 2
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#define ATA_IDENT_HEADS 6
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#define ATA_IDENT_SECTORS 12
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#define ATA_IDENT_SERIAL 20
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#define ATA_IDENT_MODEL 54
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#define ATA_IDENT_CAPABILITIES 98
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#define ATA_IDENT_FIELDVALID 106
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#define ATA_IDENT_MAX_LBA 120
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#define ATA_IDENT_COMMANDSETS 164
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#define ATA_IDENT_MAX_LBA_EXT 200
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#define IDE_ATA 0x00
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#define IDE_ATAPI 0x01
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#define ATA_REG_DATA 0x00
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#define ATA_REG_ERROR 0x01
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#define ATA_REG_FEATURES 0x01
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#define ATA_REG_SECCOUNT0 0x02
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#define ATA_REG_LBA0 0x03
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#define ATA_REG_LBA1 0x04
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#define ATA_REG_LBA2 0x05
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#define ATA_REG_HDDEVSEL 0x06
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#define ATA_REG_COMMAND 0x07
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#define ATA_REG_STATUS 0x07
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#define ATA_REG_SECCOUNT1 0x08
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#define ATA_REG_LBA3 0x09
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#define ATA_REG_LBA4 0x0A
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#define ATA_REG_LBA5 0x0B
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#define ATA_REG_CONTROL 0x0C
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#define ATA_REG_ALTSTATUS 0x0C
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#define ATA_REG_DEVADDRESS 0x0D
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NonnullRefPtr<IDEDiskDevice> IDEDiskDevice::create(DriveType type)
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{
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return adopt(*new IDEDiskDevice(type));
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}
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IDEDiskDevice::IDEDiskDevice(DriveType type)
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: IRQHandler(IRQ_FIXED_DISK)
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, m_io_base(0x1f0)
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, m_drive_type(type)
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{
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m_dma_enabled.resource() = true;
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ProcFS::the().add_sys_bool("ide_dma", m_dma_enabled);
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initialize();
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}
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IDEDiskDevice::~IDEDiskDevice()
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{
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}
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const char* IDEDiskDevice::class_name() const
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{
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return "IDEDiskDevice";
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}
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unsigned IDEDiskDevice::block_size() const
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{
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return 512;
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}
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bool IDEDiskDevice::read_blocks(unsigned index, u16 count, u8* out)
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{
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if (m_bus_master_base && m_dma_enabled.resource())
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return read_sectors_with_dma(index, count, out);
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return read_sectors(index, count, out);
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}
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bool IDEDiskDevice::read_block(unsigned index, u8* out) const
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{
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return const_cast<IDEDiskDevice*>(this)->read_blocks(index, 1, out);
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}
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bool IDEDiskDevice::write_blocks(unsigned index, u16 count, const u8* data)
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{
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if (m_bus_master_base && m_dma_enabled.resource())
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return write_sectors_with_dma(index, count, data);
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for (unsigned i = 0; i < count; ++i) {
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if (!write_sectors(index + i, 1, data + i * 512))
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return false;
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}
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return true;
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}
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bool IDEDiskDevice::write_block(unsigned index, const u8* data)
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{
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return write_blocks(index, 1, data);
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}
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static void print_ide_status(u8 status)
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{
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kprintf("DRQ=%u BSY=%u DRDY=%u DSC=%u DF=%u CORR=%u IDX=%u ERR=%u\n",
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(status & ATA_SR_DRQ) != 0,
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(status & ATA_SR_BSY) != 0,
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(status & ATA_SR_DRDY) != 0,
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(status & ATA_SR_DSC) != 0,
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(status & ATA_SR_DF) != 0,
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(status & ATA_SR_CORR) != 0,
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(status & ATA_SR_IDX) != 0,
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(status & ATA_SR_ERR) != 0);
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}
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bool IDEDiskDevice::wait_for_irq()
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{
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#ifdef DISK_DEBUG
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kprintf("disk: waiting for interrupt...\n");
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#endif
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// FIXME: Add timeout.
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while (!m_interrupted) {
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// FIXME: Put this process into a Blocked state instead, it's stupid to wake up just to check a flag.
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Scheduler::yield();
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}
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#ifdef DISK_DEBUG
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kprintf("disk: got interrupt!\n");
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#endif
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memory_barrier();
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return true;
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}
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void IDEDiskDevice::handle_irq()
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{
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u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
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if (status & ATA_SR_ERR) {
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print_ide_status(status);
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m_device_error = IO::in8(m_io_base + ATA_REG_ERROR);
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kprintf("IDEDiskDevice: Error %b!\n", m_device_error);
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} else {
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m_device_error = 0;
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}
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#ifdef DISK_DEBUG
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kprintf("disk:interrupt: DRQ=%u BSY=%u DRDY=%u\n", (status & ATA_SR_DRQ) != 0, (status & ATA_SR_BSY) != 0, (status & ATA_SR_DRDY) != 0);
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#endif
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m_interrupted = true;
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}
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void IDEDiskDevice::initialize()
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{
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static const PCI::ID piix3_ide_id = { 0x8086, 0x7010 };
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static const PCI::ID piix4_ide_id = { 0x8086, 0x7111 };
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PCI::enumerate_all([this](const PCI::Address& address, PCI::ID id) {
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if (id == piix3_ide_id || id == piix4_ide_id) {
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m_pci_address = address;
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kprintf("PIIX%u IDE device found!\n", id == piix3_ide_id ? 3 : 4);
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}
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});
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#ifdef DISK_DEBUG
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u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
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kprintf("initial status: ");
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print_ide_status(status);
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if (is_slave())
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kprintf("This IDE device is the SECONDARY device on the channel!\n");
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#endif
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m_interrupted = false;
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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enable_irq();
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u8 devsel = 0xA0;
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if (is_slave())
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devsel |= 0x10;
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IO::out8(0x1F6, devsel);
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IO::out8(0x3F6, devsel);
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IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_IDENTIFY);
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enable_irq();
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wait_for_irq();
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ByteBuffer wbuf = ByteBuffer::create_uninitialized(512);
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ByteBuffer bbuf = ByteBuffer::create_uninitialized(512);
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u8* b = bbuf.pointer();
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u16* w = (u16*)wbuf.pointer();
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const u16* wbufbase = (u16*)wbuf.pointer();
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for (u32 i = 0; i < 256; ++i) {
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u16 data = IO::in16(m_io_base + ATA_REG_DATA);
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*(w++) = data;
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*(b++) = MSB(data);
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*(b++) = LSB(data);
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}
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// "Unpad" the device name string.
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for (u32 i = 93; i > 54 && bbuf[i] == ' '; --i)
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bbuf[i] = 0;
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m_cylinders = wbufbase[1];
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m_heads = wbufbase[3];
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m_sectors_per_track = wbufbase[6];
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kprintf(
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"IDEDiskDevice: Master=\"%s\", C/H/Spt=%u/%u/%u\n",
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bbuf.pointer() + 54,
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m_cylinders,
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m_heads,
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m_sectors_per_track);
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// Let's try to set up DMA transfers.
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if (!m_pci_address.is_null()) {
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m_prdt.end_of_table = 0x8000;
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PCI::enable_bus_mastering(m_pci_address);
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m_bus_master_base = PCI::get_BAR4(m_pci_address) & 0xfffc;
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m_dma_buffer_page = MM.allocate_supervisor_physical_page();
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dbgprintf("PIIX Bus master IDE: I/O @ %x\n", m_bus_master_base);
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}
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}
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static void wait_400ns(u16 io_base)
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{
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for (int i = 0; i < 4; ++i)
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IO::in8(io_base + ATA_REG_ALTSTATUS);
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}
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bool IDEDiskDevice::read_sectors_with_dma(u32 lba, u16 count, u8* outbuf)
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{
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LOCKER(m_lock);
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#ifdef DISK_DEBUG
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dbgprintf("%s(%u): IDEDiskDevice::read_sectors_with_dma (%u x%u) -> %p\n",
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current->process().name().characters(),
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current->pid(), lba, count, outbuf);
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#endif
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disable_irq();
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m_prdt.offset = m_dma_buffer_page->paddr();
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m_prdt.size = 512 * count;
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ASSERT(m_prdt.size <= PAGE_SIZE);
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// Stop bus master
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IO::out8(m_bus_master_base, 0);
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// Write the PRDT location
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IO::out32(m_bus_master_base + 4, (u32)&m_prdt);
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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// Set transfer direction
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IO::out8(m_bus_master_base, 0x8);
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m_interrupted = false;
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enable_irq();
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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u8 devsel = 0xe0;
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if (is_slave())
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devsel |= 0x10;
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IO::out8(m_io_base + ATA_REG_CONTROL, 0);
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IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | (is_slave() << 4));
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wait_400ns(m_io_base);
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IO::out8(m_io_base + ATA_REG_FEATURES, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, 0);
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IO::out8(m_io_base + ATA_REG_LBA0, 0);
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IO::out8(m_io_base + ATA_REG_LBA1, 0);
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IO::out8(m_io_base + ATA_REG_LBA2, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, count);
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IO::out8(m_io_base + ATA_REG_LBA0, (lba & 0x000000ff) >> 0);
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IO::out8(m_io_base + ATA_REG_LBA1, (lba & 0x0000ff00) >> 8);
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IO::out8(m_io_base + ATA_REG_LBA2, (lba & 0x00ff0000) >> 16);
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for (;;) {
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auto status = IO::in8(m_io_base + ATA_REG_STATUS);
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_READ_DMA_EXT);
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wait_400ns(m_io_base);
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// Start bus master
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IO::out8(m_bus_master_base, 0x9);
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wait_for_irq();
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disable_irq();
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if (m_device_error)
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return false;
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memcpy(outbuf, m_dma_buffer_page->paddr().as_ptr(), 512 * count);
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// I read somewhere that this may trigger a cache flush so let's do it.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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return true;
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}
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bool IDEDiskDevice::read_sectors(u32 start_sector, u16 count, u8* outbuf)
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{
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ASSERT(count <= 256);
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LOCKER(m_lock);
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#ifdef DISK_DEBUG
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dbgprintf("%s: Disk::read_sectors request (%u sector(s) @ %u)\n",
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current->process().name().characters(),
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count,
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start_sector);
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#endif
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disable_irq();
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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#ifdef DISK_DEBUG
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kprintf("IDEDiskDevice: Reading %u sector(s) @ LBA %u\n", count, start_sector);
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#endif
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u8 devsel = 0xe0;
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if (is_slave())
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devsel |= 0x10;
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, count == 256 ? 0 : LSB(count));
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IO::out8(m_io_base + ATA_REG_LBA0, start_sector & 0xff);
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IO::out8(m_io_base + ATA_REG_LBA1, (start_sector >> 8) & 0xff);
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IO::out8(m_io_base + ATA_REG_LBA2, (start_sector >> 16) & 0xff);
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IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | ((start_sector >> 24) & 0xf));
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IO::out8(0x3F6, 0x08);
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while (!(IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_DRDY))
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;
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IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_READ_PIO);
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m_interrupted = false;
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enable_irq();
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wait_for_irq();
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if (m_device_error)
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return false;
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u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
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ASSERT(status & ATA_SR_DRQ);
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#ifdef DISK_DEBUG
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kprintf("Retrieving %u bytes (status=%b), outbuf=%p...\n", count * 512, status, outbuf);
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#endif
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IO::repeated_in16(m_io_base + ATA_REG_DATA, outbuf, count * 256);
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return true;
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}
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bool IDEDiskDevice::write_sectors_with_dma(u32 lba, u16 count, const u8* inbuf)
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{
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LOCKER(m_lock);
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#ifdef DISK_DEBUG
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dbgprintf("%s(%u): IDEDiskDevice::write_sectors_with_dma (%u x%u) <- %p\n",
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current->process().name().characters(),
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current->pid(), lba, count, inbuf);
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#endif
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disable_irq();
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m_prdt.offset = m_dma_buffer_page->paddr();
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m_prdt.size = 512 * count;
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memcpy(m_dma_buffer_page->paddr().as_ptr(), inbuf, 512 * count);
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ASSERT(m_prdt.size <= PAGE_SIZE);
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// Stop bus master
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IO::out8(m_bus_master_base, 0);
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// Write the PRDT location
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IO::out32(m_bus_master_base + 4, (u32)&m_prdt);
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// Turn on "Interrupt" and "Error" flag. The error flag should be cleared by hardware.
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IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
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m_interrupted = false;
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enable_irq();
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while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
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;
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u8 devsel = 0xe0;
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if (is_slave())
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devsel |= 0x10;
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IO::out8(m_io_base + ATA_REG_CONTROL, 0);
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IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | (is_slave() << 4));
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wait_400ns(m_io_base);
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IO::out8(m_io_base + ATA_REG_FEATURES, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, 0);
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IO::out8(m_io_base + ATA_REG_LBA0, 0);
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IO::out8(m_io_base + ATA_REG_LBA1, 0);
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IO::out8(m_io_base + ATA_REG_LBA2, 0);
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IO::out8(m_io_base + ATA_REG_SECCOUNT0, count);
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IO::out8(m_io_base + ATA_REG_LBA0, (lba & 0x000000ff) >> 0);
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IO::out8(m_io_base + ATA_REG_LBA1, (lba & 0x0000ff00) >> 8);
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IO::out8(m_io_base + ATA_REG_LBA2, (lba & 0x00ff0000) >> 16);
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for (;;) {
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auto status = IO::in8(m_io_base + ATA_REG_STATUS);
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if (!(status & ATA_SR_BSY) && (status & ATA_SR_DRDY))
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break;
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}
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|
|
IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_WRITE_DMA_EXT);
|
|
wait_400ns(m_io_base);
|
|
|
|
// Start bus master
|
|
IO::out8(m_bus_master_base, 0x1);
|
|
|
|
wait_for_irq();
|
|
disable_irq();
|
|
|
|
if (m_device_error)
|
|
return false;
|
|
|
|
// I read somewhere that this may trigger a cache flush so let's do it.
|
|
IO::out8(m_bus_master_base + 2, IO::in8(m_bus_master_base + 2) | 0x6);
|
|
return true;
|
|
}
|
|
|
|
bool IDEDiskDevice::write_sectors(u32 start_sector, u16 count, const u8* data)
|
|
{
|
|
ASSERT(count <= 256);
|
|
LOCKER(m_lock);
|
|
#ifdef DISK_DEBUG
|
|
dbgprintf("%s(%u): IDEDiskDevice::write_sectors request (%u sector(s) @ %u)\n",
|
|
current->process().name().characters(),
|
|
current->pid(),
|
|
count,
|
|
start_sector);
|
|
#endif
|
|
disable_irq();
|
|
|
|
while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
|
|
;
|
|
|
|
//dbgprintf("IDEDiskDevice: Writing %u sector(s) @ LBA %u\n", count, start_sector);
|
|
|
|
u8 devsel = 0xe0;
|
|
if (is_slave())
|
|
devsel |= 0x10;
|
|
|
|
IO::out8(m_io_base + ATA_REG_SECCOUNT0, count == 256 ? 0 : LSB(count));
|
|
IO::out8(m_io_base + ATA_REG_LBA0, start_sector & 0xff);
|
|
IO::out8(m_io_base + ATA_REG_LBA1, (start_sector >> 8) & 0xff);
|
|
IO::out8(m_io_base + ATA_REG_LBA2, (start_sector >> 16) & 0xff);
|
|
IO::out8(m_io_base + ATA_REG_HDDEVSEL, devsel | ((start_sector >> 24) & 0xf));
|
|
|
|
IO::out8(0x3F6, 0x08);
|
|
|
|
IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_WRITE_PIO);
|
|
|
|
while (!(IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_DRQ))
|
|
;
|
|
|
|
u8 status = IO::in8(m_io_base + ATA_REG_STATUS);
|
|
ASSERT(status & ATA_SR_DRQ);
|
|
IO::repeated_out16(m_io_base + ATA_REG_DATA, data, count * 256);
|
|
|
|
m_interrupted = false;
|
|
enable_irq();
|
|
wait_for_irq();
|
|
|
|
disable_irq();
|
|
IO::out8(m_io_base + ATA_REG_COMMAND, ATA_CMD_CACHE_FLUSH);
|
|
while (IO::in8(m_io_base + ATA_REG_STATUS) & ATA_SR_BSY)
|
|
;
|
|
m_interrupted = false;
|
|
enable_irq();
|
|
wait_for_irq();
|
|
|
|
return !m_device_error;
|
|
}
|
|
|
|
bool IDEDiskDevice::is_slave() const
|
|
{
|
|
return m_drive_type == DriveType::SLAVE;
|
|
}
|