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b18bf702ea
This adds a shader processor that executes our ISA when a fragment shader is currently bound to the device.
116 lines
4.8 KiB
C++
116 lines
4.8 KiB
C++
/*
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* Copyright (c) 2022, Stephan Unverwerth <s.unverwerth@serenityos.org>
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*
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* SPDX-License-Identifier: BSD-2-Clause
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*/
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#include <LibGfx/Vector2.h>
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#include <LibGfx/Vector4.h>
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#include <LibSoftGPU/Shader.h>
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#include <LibSoftGPU/ShaderProcessor.h>
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namespace SoftGPU {
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using AK::SIMD::f32x4;
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void ShaderProcessor::execute(PixelQuad& quad, Shader const& shader)
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{
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auto& instructions = shader.instructions();
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for (size_t program_counter = 0; program_counter < instructions.size(); ++program_counter) {
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auto instruction = instructions[program_counter];
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switch (instruction.operation) {
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case Opcode::Input:
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op_input(quad, instruction.arguments);
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break;
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case Opcode::Output:
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op_output(quad, instruction.arguments);
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break;
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case Opcode::Sample2D:
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op_sample2d(instruction.arguments);
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break;
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case Opcode::Swizzle:
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op_swizzle(instruction.arguments);
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break;
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case Opcode::Add:
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op_add(instruction.arguments);
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break;
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case Opcode::Sub:
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op_sub(instruction.arguments);
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break;
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case Opcode::Mul:
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op_mul(instruction.arguments);
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break;
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case Opcode::Div:
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op_div(instruction.arguments);
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break;
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default:
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VERIFY_NOT_REACHED();
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}
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}
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}
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void ShaderProcessor::op_input(PixelQuad const& quad, Instruction::Arguments arguments)
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{
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set_register(arguments.input.target_register, quad.get_input_float(arguments.input.input_index));
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set_register(arguments.input.target_register + 1, quad.get_input_float(arguments.input.input_index + 1));
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set_register(arguments.input.target_register + 2, quad.get_input_float(arguments.input.input_index + 2));
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set_register(arguments.input.target_register + 3, quad.get_input_float(arguments.input.input_index + 3));
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}
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void ShaderProcessor::op_output(PixelQuad& quad, Instruction::Arguments arguments)
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{
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quad.set_output(arguments.output.output_index, get_register(arguments.output.source_register));
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quad.set_output(arguments.output.output_index + 1, get_register(arguments.output.source_register + 1));
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quad.set_output(arguments.output.output_index + 2, get_register(arguments.output.source_register + 2));
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quad.set_output(arguments.output.output_index + 3, get_register(arguments.output.source_register + 3));
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}
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void ShaderProcessor::op_sample2d(Instruction::Arguments arguments)
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{
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Vector2<AK::SIMD::f32x4> coordinates = {
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get_register(arguments.sample.coordinates_register),
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get_register(arguments.sample.coordinates_register + 1),
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};
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auto sample = m_samplers[arguments.sample.sampler_index].sample_2d(coordinates);
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set_register(arguments.sample.target_register, sample.x());
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set_register(arguments.sample.target_register + 1, sample.y());
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set_register(arguments.sample.target_register + 2, sample.z());
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set_register(arguments.sample.target_register + 3, sample.w());
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}
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void ShaderProcessor::op_swizzle(Instruction::Arguments arguments)
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{
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f32x4 inputs[] {
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get_register(arguments.swizzle.source_register),
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get_register(arguments.swizzle.source_register + 1),
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get_register(arguments.swizzle.source_register + 2),
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get_register(arguments.swizzle.source_register + 3)
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};
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set_register(arguments.swizzle.target_register, inputs[swizzle_index(arguments.swizzle.pattern, 0)]);
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set_register(arguments.swizzle.target_register + 1, inputs[swizzle_index(arguments.swizzle.pattern, 1)]);
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set_register(arguments.swizzle.target_register + 2, inputs[swizzle_index(arguments.swizzle.pattern, 2)]);
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set_register(arguments.swizzle.target_register + 3, inputs[swizzle_index(arguments.swizzle.pattern, 3)]);
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}
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#define SHADER_BINOP(NAME, OP) \
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void ShaderProcessor::op_##NAME(Instruction::Arguments arguments) \
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{ \
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auto const target = arguments.binop.target_register; \
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auto const source1 = arguments.binop.source_register1; \
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auto const source2 = arguments.binop.source_register2; \
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set_register(target, get_register(source1) OP get_register(source2)); \
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set_register(target + 1, get_register(source1 + 1) OP get_register(source2 + 1)); \
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set_register(target + 2, get_register(source1 + 2) OP get_register(source2 + 2)); \
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set_register(target + 3, get_register(source1 + 3) OP get_register(source2 + 3)); \
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}
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SHADER_BINOP(add, +)
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SHADER_BINOP(sub, -)
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SHADER_BINOP(mul, *)
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SHADER_BINOP(div, /)
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#undef SHADER_BINOP
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}
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