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https://github.com/LadybirdBrowser/ladybird.git
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b02d33bd63
We need to halt the BSP briefly until all APs are ready for the first context switch, but we can't hold the same spinlock by all of them while doing so. So, while the APs are waiting on each other they need to release the scheduler lock, and then once signaled re-acquire it. Should solve some timing dependent hangs or crashes, most easily observed using qemu with kvm disabled.
118 lines
3.8 KiB
C++
118 lines
3.8 KiB
C++
/*
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* Copyright (c) 2018-2020, Andreas Kling <kling@serenityos.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#pragma once
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#include <AK/Types.h>
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#include <Kernel/VM/MemoryManager.h>
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namespace Kernel {
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struct LocalAPIC {
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u32 apic_id;
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};
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class APIC {
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public:
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static APIC& the();
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static void initialize();
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static bool initialized();
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bool init_bsp();
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void eoi();
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void boot_aps();
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void enable(u32 cpu);
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void init_finished(u32 cpu);
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void broadcast_ipi();
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void send_ipi(u32 cpu);
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static u8 spurious_interrupt_vector();
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Thread* get_idle_thread(u32 cpu) const;
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u32 enabled_processor_count() const { return m_processor_enabled_cnt; }
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private:
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class ICRReg {
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u32 m_low { 0 };
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u32 m_high { 0 };
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public:
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enum DeliveryMode {
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Fixed = 0x0,
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LowPriority = 0x1,
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SMI = 0x2,
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NMI = 0x4,
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INIT = 0x5,
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StartUp = 0x6,
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};
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enum DestinationMode {
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Physical = 0x0,
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Logical = 0x1,
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};
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enum Level {
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DeAssert = 0x0,
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Assert = 0x1
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};
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enum class TriggerMode {
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Edge = 0x0,
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Level = 0x1,
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};
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enum DestinationShorthand {
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NoShorthand = 0x0,
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Self = 0x1,
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AllIncludingSelf = 0x2,
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AllExcludingSelf = 0x3,
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};
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ICRReg(u8 vector, DeliveryMode delivery_mode, DestinationMode destination_mode, Level level, TriggerMode trigger_mode, DestinationShorthand destinationShort, u8 destination = 0)
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: m_low(vector | (delivery_mode << 8) | (destination_mode << 11) | (level << 14) | (static_cast<u32>(trigger_mode) << 15) | (destinationShort << 18)),
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m_high((u32)destination << 24)
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{
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}
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u32 low() const { return m_low; }
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u32 high() const { return m_high; }
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};
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OwnPtr<Region> m_apic_base;
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Vector<OwnPtr<Processor>> m_ap_processor_info;
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Vector<Thread*> m_ap_idle_threads;
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AK::Atomic<u8> m_apic_ap_count{0};
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AK::Atomic<u8> m_apic_ap_continue{0};
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u32 m_processor_cnt{0};
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u32 m_processor_enabled_cnt{0};
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static PhysicalAddress get_base();
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static void set_base(const PhysicalAddress& base);
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void write_register(u32 offset, u32 value);
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u32 read_register(u32 offset);
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void set_lvt(u32 offset, u8 interrupt);
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void set_siv(u32 offset, u8 interrupt);
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void wait_for_pending_icr();
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void write_icr(const ICRReg& icr);
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void do_boot_aps();
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};
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}
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