mirror of
https://github.com/ProvableHQ/leo.git
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d44457fc32
* bump snarkvm rev * update default gitignore * impl leo execute * bump snarkvm 0.14.5 * modify examples wip * update run.sh examples * impl env file * clippy warning * fix auction example * fix auction example env * generate new private key for new env - tests failing due to env not found err * commit error changes * Fix tests; clippy * Get examples working * leo build checks that build dir is well formed; clippy * Clean up * Update examples/README.md Co-authored-by: d0cd <pranavsaig@gmail.com> Signed-off-by: Collin Chin <16715212+collinc97@users.noreply.github.com> * do not commit .avm files * use snarkvm commands --------- Signed-off-by: Collin Chin <16715212+collinc97@users.noreply.github.com> Co-authored-by: Pranav Gaddamadugu <pranav@aleo.org> Co-authored-by: d0cd <pranavsaig@gmail.com>
562 lines
16 KiB
Plaintext
562 lines
16 KiB
Plaintext
program basic_bank.aleo;
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record Token:
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owner as address.private;
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amount as u64.private;
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mapping balances:
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key left as field.public;
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value right as u64.public;
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function issue:
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input r0 as address.private;
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input r1 as u64.private;
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assert.eq self.caller aleo1t0uer3jgtsgmx5tq6x6f9ecu8tr57rzzfnc2dgmcqldceal0ls9qf6st7a;
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cast r0 r1 into r2 as Token.record;
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output r2 as Token.record;
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function deposit:
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input r0 as Token.record;
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input r1 as u64.private;
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sub r0.amount r1 into r2;
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cast r0.owner r2 into r3 as Token.record;
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hash.bhp256 r0.owner into r4 as field; output r3 as Token.record;
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finalize r4 r1;
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finalize deposit:
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input r0 as field.public;
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input r1 as u64.public;
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get.or_use balances[r0] 0u64 into r2;
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add r2 r1 into r3;
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set r3 into balances[r0];
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closure calculate_interest:
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input r0 as u64;
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input r1 as u64;
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input r2 as u64;
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lt 0u64 r2 into r3;
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mul r0 r1 into r4;
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div r4 10000u64 into r5;
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add r0 r5 into r6;
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ternary r3 r6 r0 into r7;
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lt 1u64 r2 into r8;
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mul r7 r1 into r9;
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div r9 10000u64 into r10;
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add r7 r10 into r11;
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ternary r8 r11 r7 into r12;
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lt 2u64 r2 into r13;
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mul r12 r1 into r14;
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div r14 10000u64 into r15;
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add r12 r15 into r16;
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ternary r13 r16 r12 into r17;
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lt 3u64 r2 into r18;
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mul r17 r1 into r19;
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div r19 10000u64 into r20;
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add r17 r20 into r21;
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ternary r18 r21 r17 into r22;
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lt 4u64 r2 into r23;
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mul r22 r1 into r24;
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div r24 10000u64 into r25;
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add r22 r25 into r26;
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ternary r23 r26 r22 into r27;
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lt 5u64 r2 into r28;
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mul r27 r1 into r29;
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div r29 10000u64 into r30;
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add r27 r30 into r31;
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ternary r28 r31 r27 into r32;
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lt 6u64 r2 into r33;
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mul r32 r1 into r34;
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div r34 10000u64 into r35;
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add r32 r35 into r36;
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ternary r33 r36 r32 into r37;
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lt 7u64 r2 into r38;
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mul r37 r1 into r39;
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div r39 10000u64 into r40;
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add r37 r40 into r41;
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ternary r38 r41 r37 into r42;
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lt 8u64 r2 into r43;
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mul r42 r1 into r44;
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div r44 10000u64 into r45;
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add r42 r45 into r46;
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ternary r43 r46 r42 into r47;
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lt 9u64 r2 into r48;
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mul r47 r1 into r49;
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div r49 10000u64 into r50;
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add r47 r50 into r51;
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ternary r48 r51 r47 into r52;
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lt 10u64 r2 into r53;
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mul r52 r1 into r54;
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div r54 10000u64 into r55;
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add r52 r55 into r56;
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ternary r53 r56 r52 into r57;
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lt 11u64 r2 into r58;
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mul r57 r1 into r59;
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div r59 10000u64 into r60;
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add r57 r60 into r61;
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ternary r58 r61 r57 into r62;
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lt 12u64 r2 into r63;
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mul r62 r1 into r64;
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div r64 10000u64 into r65;
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add r62 r65 into r66;
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ternary r63 r66 r62 into r67;
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lt 13u64 r2 into r68;
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mul r67 r1 into r69;
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div r69 10000u64 into r70;
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add r67 r70 into r71;
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ternary r68 r71 r67 into r72;
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lt 14u64 r2 into r73;
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mul r72 r1 into r74;
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div r74 10000u64 into r75;
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add r72 r75 into r76;
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ternary r73 r76 r72 into r77;
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lt 15u64 r2 into r78;
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mul r77 r1 into r79;
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div r79 10000u64 into r80;
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add r77 r80 into r81;
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ternary r78 r81 r77 into r82;
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lt 16u64 r2 into r83;
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mul r82 r1 into r84;
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div r84 10000u64 into r85;
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add r82 r85 into r86;
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ternary r83 r86 r82 into r87;
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lt 17u64 r2 into r88;
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mul r87 r1 into r89;
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div r89 10000u64 into r90;
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add r87 r90 into r91;
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ternary r88 r91 r87 into r92;
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lt 18u64 r2 into r93;
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mul r92 r1 into r94;
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div r94 10000u64 into r95;
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add r92 r95 into r96;
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ternary r93 r96 r92 into r97;
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lt 19u64 r2 into r98;
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mul r97 r1 into r99;
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div r99 10000u64 into r100;
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add r97 r100 into r101;
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ternary r98 r101 r97 into r102;
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lt 20u64 r2 into r103;
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mul r102 r1 into r104;
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div r104 10000u64 into r105;
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add r102 r105 into r106;
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ternary r103 r106 r102 into r107;
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lt 21u64 r2 into r108;
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mul r107 r1 into r109;
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div r109 10000u64 into r110;
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add r107 r110 into r111;
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ternary r108 r111 r107 into r112;
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lt 22u64 r2 into r113;
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mul r112 r1 into r114;
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div r114 10000u64 into r115;
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add r112 r115 into r116;
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ternary r113 r116 r112 into r117;
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lt 23u64 r2 into r118;
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mul r117 r1 into r119;
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div r119 10000u64 into r120;
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add r117 r120 into r121;
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ternary r118 r121 r117 into r122;
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lt 24u64 r2 into r123;
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mul r122 r1 into r124;
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div r124 10000u64 into r125;
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add r122 r125 into r126;
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ternary r123 r126 r122 into r127;
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lt 25u64 r2 into r128;
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mul r127 r1 into r129;
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div r129 10000u64 into r130;
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add r127 r130 into r131;
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ternary r128 r131 r127 into r132;
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lt 26u64 r2 into r133;
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mul r132 r1 into r134;
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div r134 10000u64 into r135;
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add r132 r135 into r136;
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ternary r133 r136 r132 into r137;
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lt 27u64 r2 into r138;
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mul r137 r1 into r139;
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div r139 10000u64 into r140;
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add r137 r140 into r141;
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ternary r138 r141 r137 into r142;
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lt 28u64 r2 into r143;
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mul r142 r1 into r144;
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div r144 10000u64 into r145;
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add r142 r145 into r146;
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ternary r143 r146 r142 into r147;
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lt 29u64 r2 into r148;
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mul r147 r1 into r149;
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div r149 10000u64 into r150;
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add r147 r150 into r151;
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ternary r148 r151 r147 into r152;
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lt 30u64 r2 into r153;
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mul r152 r1 into r154;
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div r154 10000u64 into r155;
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add r152 r155 into r156;
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ternary r153 r156 r152 into r157;
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lt 31u64 r2 into r158;
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mul r157 r1 into r159;
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div r159 10000u64 into r160;
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add r157 r160 into r161;
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ternary r158 r161 r157 into r162;
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lt 32u64 r2 into r163;
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mul r162 r1 into r164;
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div r164 10000u64 into r165;
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add r162 r165 into r166;
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ternary r163 r166 r162 into r167;
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lt 33u64 r2 into r168;
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mul r167 r1 into r169;
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div r169 10000u64 into r170;
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add r167 r170 into r171;
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ternary r168 r171 r167 into r172;
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lt 34u64 r2 into r173;
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mul r172 r1 into r174;
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div r174 10000u64 into r175;
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add r172 r175 into r176;
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ternary r173 r176 r172 into r177;
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lt 35u64 r2 into r178;
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mul r177 r1 into r179;
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div r179 10000u64 into r180;
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add r177 r180 into r181;
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ternary r178 r181 r177 into r182;
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lt 36u64 r2 into r183;
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mul r182 r1 into r184;
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div r184 10000u64 into r185;
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add r182 r185 into r186;
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ternary r183 r186 r182 into r187;
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lt 37u64 r2 into r188;
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mul r187 r1 into r189;
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div r189 10000u64 into r190;
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add r187 r190 into r191;
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ternary r188 r191 r187 into r192;
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lt 38u64 r2 into r193;
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mul r192 r1 into r194;
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div r194 10000u64 into r195;
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add r192 r195 into r196;
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ternary r193 r196 r192 into r197;
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lt 39u64 r2 into r198;
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mul r197 r1 into r199;
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div r199 10000u64 into r200;
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add r197 r200 into r201;
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ternary r198 r201 r197 into r202;
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lt 40u64 r2 into r203;
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mul r202 r1 into r204;
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div r204 10000u64 into r205;
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add r202 r205 into r206;
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ternary r203 r206 r202 into r207;
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lt 41u64 r2 into r208;
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mul r207 r1 into r209;
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div r209 10000u64 into r210;
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add r207 r210 into r211;
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ternary r208 r211 r207 into r212;
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lt 42u64 r2 into r213;
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mul r212 r1 into r214;
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div r214 10000u64 into r215;
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add r212 r215 into r216;
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ternary r213 r216 r212 into r217;
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lt 43u64 r2 into r218;
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mul r217 r1 into r219;
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div r219 10000u64 into r220;
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add r217 r220 into r221;
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ternary r218 r221 r217 into r222;
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lt 44u64 r2 into r223;
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mul r222 r1 into r224;
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div r224 10000u64 into r225;
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add r222 r225 into r226;
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ternary r223 r226 r222 into r227;
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lt 45u64 r2 into r228;
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mul r227 r1 into r229;
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div r229 10000u64 into r230;
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add r227 r230 into r231;
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ternary r228 r231 r227 into r232;
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lt 46u64 r2 into r233;
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mul r232 r1 into r234;
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div r234 10000u64 into r235;
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add r232 r235 into r236;
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ternary r233 r236 r232 into r237;
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lt 47u64 r2 into r238;
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mul r237 r1 into r239;
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div r239 10000u64 into r240;
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add r237 r240 into r241;
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ternary r238 r241 r237 into r242;
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lt 48u64 r2 into r243;
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mul r242 r1 into r244;
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div r244 10000u64 into r245;
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add r242 r245 into r246;
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ternary r243 r246 r242 into r247;
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lt 49u64 r2 into r248;
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mul r247 r1 into r249;
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div r249 10000u64 into r250;
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add r247 r250 into r251;
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ternary r248 r251 r247 into r252;
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lt 50u64 r2 into r253;
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mul r252 r1 into r254;
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div r254 10000u64 into r255;
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add r252 r255 into r256;
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ternary r253 r256 r252 into r257;
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lt 51u64 r2 into r258;
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mul r257 r1 into r259;
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div r259 10000u64 into r260;
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add r257 r260 into r261;
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ternary r258 r261 r257 into r262;
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lt 52u64 r2 into r263;
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mul r262 r1 into r264;
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div r264 10000u64 into r265;
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add r262 r265 into r266;
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ternary r263 r266 r262 into r267;
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lt 53u64 r2 into r268;
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mul r267 r1 into r269;
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div r269 10000u64 into r270;
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add r267 r270 into r271;
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ternary r268 r271 r267 into r272;
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lt 54u64 r2 into r273;
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mul r272 r1 into r274;
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div r274 10000u64 into r275;
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add r272 r275 into r276;
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ternary r273 r276 r272 into r277;
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lt 55u64 r2 into r278;
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mul r277 r1 into r279;
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div r279 10000u64 into r280;
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add r277 r280 into r281;
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ternary r278 r281 r277 into r282;
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lt 56u64 r2 into r283;
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mul r282 r1 into r284;
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div r284 10000u64 into r285;
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add r282 r285 into r286;
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ternary r283 r286 r282 into r287;
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lt 57u64 r2 into r288;
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mul r287 r1 into r289;
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div r289 10000u64 into r290;
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add r287 r290 into r291;
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ternary r288 r291 r287 into r292;
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lt 58u64 r2 into r293;
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mul r292 r1 into r294;
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div r294 10000u64 into r295;
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add r292 r295 into r296;
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ternary r293 r296 r292 into r297;
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lt 59u64 r2 into r298;
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mul r297 r1 into r299;
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div r299 10000u64 into r300;
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add r297 r300 into r301;
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ternary r298 r301 r297 into r302;
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lt 60u64 r2 into r303;
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mul r302 r1 into r304;
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div r304 10000u64 into r305;
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add r302 r305 into r306;
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ternary r303 r306 r302 into r307;
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lt 61u64 r2 into r308;
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mul r307 r1 into r309;
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div r309 10000u64 into r310;
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add r307 r310 into r311;
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ternary r308 r311 r307 into r312;
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lt 62u64 r2 into r313;
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mul r312 r1 into r314;
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div r314 10000u64 into r315;
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add r312 r315 into r316;
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ternary r313 r316 r312 into r317;
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lt 63u64 r2 into r318;
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mul r317 r1 into r319;
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div r319 10000u64 into r320;
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add r317 r320 into r321;
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ternary r318 r321 r317 into r322;
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lt 64u64 r2 into r323;
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mul r322 r1 into r324;
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div r324 10000u64 into r325;
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add r322 r325 into r326;
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ternary r323 r326 r322 into r327;
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lt 65u64 r2 into r328;
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mul r327 r1 into r329;
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div r329 10000u64 into r330;
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add r327 r330 into r331;
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ternary r328 r331 r327 into r332;
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lt 66u64 r2 into r333;
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mul r332 r1 into r334;
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div r334 10000u64 into r335;
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add r332 r335 into r336;
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ternary r333 r336 r332 into r337;
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lt 67u64 r2 into r338;
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mul r337 r1 into r339;
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div r339 10000u64 into r340;
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add r337 r340 into r341;
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ternary r338 r341 r337 into r342;
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lt 68u64 r2 into r343;
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mul r342 r1 into r344;
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div r344 10000u64 into r345;
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add r342 r345 into r346;
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ternary r343 r346 r342 into r347;
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lt 69u64 r2 into r348;
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mul r347 r1 into r349;
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div r349 10000u64 into r350;
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add r347 r350 into r351;
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ternary r348 r351 r347 into r352;
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lt 70u64 r2 into r353;
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mul r352 r1 into r354;
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div r354 10000u64 into r355;
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add r352 r355 into r356;
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ternary r353 r356 r352 into r357;
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lt 71u64 r2 into r358;
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mul r357 r1 into r359;
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div r359 10000u64 into r360;
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add r357 r360 into r361;
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ternary r358 r361 r357 into r362;
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lt 72u64 r2 into r363;
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mul r362 r1 into r364;
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div r364 10000u64 into r365;
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add r362 r365 into r366;
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ternary r363 r366 r362 into r367;
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lt 73u64 r2 into r368;
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mul r367 r1 into r369;
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div r369 10000u64 into r370;
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add r367 r370 into r371;
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ternary r368 r371 r367 into r372;
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lt 74u64 r2 into r373;
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mul r372 r1 into r374;
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div r374 10000u64 into r375;
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add r372 r375 into r376;
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ternary r373 r376 r372 into r377;
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lt 75u64 r2 into r378;
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mul r377 r1 into r379;
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div r379 10000u64 into r380;
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add r377 r380 into r381;
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ternary r378 r381 r377 into r382;
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lt 76u64 r2 into r383;
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mul r382 r1 into r384;
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div r384 10000u64 into r385;
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add r382 r385 into r386;
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ternary r383 r386 r382 into r387;
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lt 77u64 r2 into r388;
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mul r387 r1 into r389;
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div r389 10000u64 into r390;
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add r387 r390 into r391;
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ternary r388 r391 r387 into r392;
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lt 78u64 r2 into r393;
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mul r392 r1 into r394;
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div r394 10000u64 into r395;
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add r392 r395 into r396;
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ternary r393 r396 r392 into r397;
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lt 79u64 r2 into r398;
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mul r397 r1 into r399;
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div r399 10000u64 into r400;
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add r397 r400 into r401;
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ternary r398 r401 r397 into r402;
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lt 80u64 r2 into r403;
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mul r402 r1 into r404;
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div r404 10000u64 into r405;
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add r402 r405 into r406;
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ternary r403 r406 r402 into r407;
|
|
lt 81u64 r2 into r408;
|
|
mul r407 r1 into r409;
|
|
div r409 10000u64 into r410;
|
|
add r407 r410 into r411;
|
|
ternary r408 r411 r407 into r412;
|
|
lt 82u64 r2 into r413;
|
|
mul r412 r1 into r414;
|
|
div r414 10000u64 into r415;
|
|
add r412 r415 into r416;
|
|
ternary r413 r416 r412 into r417;
|
|
lt 83u64 r2 into r418;
|
|
mul r417 r1 into r419;
|
|
div r419 10000u64 into r420;
|
|
add r417 r420 into r421;
|
|
ternary r418 r421 r417 into r422;
|
|
lt 84u64 r2 into r423;
|
|
mul r422 r1 into r424;
|
|
div r424 10000u64 into r425;
|
|
add r422 r425 into r426;
|
|
ternary r423 r426 r422 into r427;
|
|
lt 85u64 r2 into r428;
|
|
mul r427 r1 into r429;
|
|
div r429 10000u64 into r430;
|
|
add r427 r430 into r431;
|
|
ternary r428 r431 r427 into r432;
|
|
lt 86u64 r2 into r433;
|
|
mul r432 r1 into r434;
|
|
div r434 10000u64 into r435;
|
|
add r432 r435 into r436;
|
|
ternary r433 r436 r432 into r437;
|
|
lt 87u64 r2 into r438;
|
|
mul r437 r1 into r439;
|
|
div r439 10000u64 into r440;
|
|
add r437 r440 into r441;
|
|
ternary r438 r441 r437 into r442;
|
|
lt 88u64 r2 into r443;
|
|
mul r442 r1 into r444;
|
|
div r444 10000u64 into r445;
|
|
add r442 r445 into r446;
|
|
ternary r443 r446 r442 into r447;
|
|
lt 89u64 r2 into r448;
|
|
mul r447 r1 into r449;
|
|
div r449 10000u64 into r450;
|
|
add r447 r450 into r451;
|
|
ternary r448 r451 r447 into r452;
|
|
lt 90u64 r2 into r453;
|
|
mul r452 r1 into r454;
|
|
div r454 10000u64 into r455;
|
|
add r452 r455 into r456;
|
|
ternary r453 r456 r452 into r457;
|
|
lt 91u64 r2 into r458;
|
|
mul r457 r1 into r459;
|
|
div r459 10000u64 into r460;
|
|
add r457 r460 into r461;
|
|
ternary r458 r461 r457 into r462;
|
|
lt 92u64 r2 into r463;
|
|
mul r462 r1 into r464;
|
|
div r464 10000u64 into r465;
|
|
add r462 r465 into r466;
|
|
ternary r463 r466 r462 into r467;
|
|
lt 93u64 r2 into r468;
|
|
mul r467 r1 into r469;
|
|
div r469 10000u64 into r470;
|
|
add r467 r470 into r471;
|
|
ternary r468 r471 r467 into r472;
|
|
lt 94u64 r2 into r473;
|
|
mul r472 r1 into r474;
|
|
div r474 10000u64 into r475;
|
|
add r472 r475 into r476;
|
|
ternary r473 r476 r472 into r477;
|
|
lt 95u64 r2 into r478;
|
|
mul r477 r1 into r479;
|
|
div r479 10000u64 into r480;
|
|
add r477 r480 into r481;
|
|
ternary r478 r481 r477 into r482;
|
|
lt 96u64 r2 into r483;
|
|
mul r482 r1 into r484;
|
|
div r484 10000u64 into r485;
|
|
add r482 r485 into r486;
|
|
ternary r483 r486 r482 into r487;
|
|
lt 97u64 r2 into r488;
|
|
mul r487 r1 into r489;
|
|
div r489 10000u64 into r490;
|
|
add r487 r490 into r491;
|
|
ternary r488 r491 r487 into r492;
|
|
lt 98u64 r2 into r493;
|
|
mul r492 r1 into r494;
|
|
div r494 10000u64 into r495;
|
|
add r492 r495 into r496;
|
|
ternary r493 r496 r492 into r497;
|
|
lt 99u64 r2 into r498;
|
|
mul r497 r1 into r499;
|
|
div r499 10000u64 into r500;
|
|
add r497 r500 into r501;
|
|
ternary r498 r501 r497 into r502;
|
|
output r502 as u64;
|
|
|
|
|
|
function withdraw:
|
|
input r0 as address.private;
|
|
input r1 as u64.private;
|
|
input r2 as u64.private;
|
|
input r3 as u64.private;
|
|
assert.eq self.caller aleo1t0uer3jgtsgmx5tq6x6f9ecu8tr57rzzfnc2dgmcqldceal0ls9qf6st7a;
|
|
hash.bhp256 r0 into r4 as field; call calculate_interest r1 r2 r3 into r5;
|
|
cast r0 r5 into r6 as Token.record;
|
|
output r6 as Token.record;
|
|
|
|
finalize r4 r1;
|
|
|
|
finalize withdraw:
|
|
input r0 as field.public;
|
|
input r1 as u64.public;
|
|
get.or_use balances[r0] 0u64 into r2;
|
|
sub r2 r1 into r3;
|
|
set r3 into balances[r0];
|