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Add Verilog syntax test file
commitc18afcb01a2bd6561381d4bd301a3cb1fcd5d5f8 authorMohamed Abdelnour <mohamed.k.abdelnour@gmail.com> dateSun 30 May 2021, 10:49 (5 years ago) parent63043d4
3 files changed+549
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unifiedsplit
tests/syntax-tests/highlighted/Verilog/div_pipelined.v+172 tests/syntax-tests/source/Verilog/LICENSE.md+205 tests/syntax-tests/source/Verilog/div_pipelined.v+172
tests/syntax-tests/highlighted/Verilog/div_pipelined.vnew file+172
@@ -0,0 +1,172 @@
1+// Copyright 2018 Schuyler Eldridge
2+//
3+// Licensed under the Apache License, Version 2.0 (the "License");
4+// you may not use this file except in compliance with the License.
5+// You may obtain a copy of the License at
6+//
7+// http://www.apache.org/licenses/LICENSE-2.0
8+//
9+// Unless required by applicable law or agreed to in writing, software
10+// distributed under the License is distributed on an "AS IS" BASIS,
11+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+// See the License for the specific language governing permissions and
13+// limitations under the License.
14+
15+// Implements a fixed-point parameterized pipelined division
16+// operation. Outputs are expected to be on range [-1,1), techincally
17+// [-1,2^(BITS-1)-1/2^(BITS-1)]. There is no convergent rounding.
18+//
19+// [TODO] Implement optional convergent rounding and some form of
20+// variable output binary point placement. There are arguments in
21+// these changes that make sense (specifically, adding an additional
22+// bit results in a gain of one value when all the other 2^6 values
23+// greater than 1 aren't used). Other improvements that are needed: 1)
24+// quotient_gen is getting smaller by one bit in every stage, it would
25+// make more sense to generate this as such, 2) there's some weird
26+// initial behavior after rst_n is deasserted, you get weird output on
27+// the quotient line for a number of cycles.
28+//
29+// [TODO] This doesn't exactly behave as expected if you specify
30+// different BITS and STAGES parameters (which for a functional
31+// module, should be implemented). Note, that this technically works,
32+// but needs more investigation to fully understand its properties.
33+
34+`timescale 1ns / 1ps
35+module div_pipelined
36+ (
37+ input clk,
38+ input rst_n,
39+ input start,
40+ input [BITS-1:0] dividend,
41+ input [BITS-1:0] divisor,
42+ output reg data_valid,
43+ output reg div_by_zero,
44+ output reg [STAGES-1:0] quotient
45+ // output reg [7:0] quotient_correct
46+ );
47+
48+ // WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
49+ // LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
50+ // OVERWRITTEN!
51+ parameter
52+ BITS = 8,
53+ STAGES = BITS;
54+
55+ // y = a/bQ
56+
57+ reg [STAGES-1:0] start_gen, negative_quotient_gen, div_by_zero_gen;
58+ reg [BITS*2*(STAGES-1)-1:0] dividend_gen, divisor_gen, quotient_gen;
59+ wire [BITS-1:0] pad_dividend;
60+ wire [BITS-2:0] pad_divisor;
61+
62+ assign pad_dividend = 0;
63+ assign pad_divisor = 0;
64+
65+ // sign conversion stage
66+ always @ (posedge clk or negedge rst_n)
67+ begin
68+ if (!rst_n) begin
69+ div_by_zero_gen[0] <= 0;
70+ start_gen[0] <=0;
71+ negative_quotient_gen[0] <= 0;
72+ dividend_gen[BITS*2-1:0] <= 0;
73+ divisor_gen[BITS*2-1:0] <= 0; end
74+ else begin
75+ div_by_zero_gen[0] <= (divisor == 0);
76+ start_gen[0] <= start;
77+ negative_quotient_gen[0] <= dividend[BITS-1] ^ divisor[BITS-1];
78+ dividend_gen[BITS*2-1:0] <= (dividend[BITS-1]) ? ~{dividend,pad_dividend} + 1 : {dividend,pad_dividend};
79+ divisor_gen[BITS*2-1:0] <= (divisor [BITS-1]) ? ~{1'b1,divisor, pad_divisor} + 1 : {1'b0,divisor, pad_divisor};
80+ end
81+ end
82+
83+ // first computation stage
84+ always @ (posedge clk or negedge rst_n) begin
85+ if (!rst_n) begin
86+ div_by_zero_gen[1] <= 0;
87+ start_gen[1] <= 0;
88+ negative_quotient_gen[1] <= 0;
89+ divisor_gen[BITS*2*2-1:BITS*2] <= 0;
90+ quotient_gen[BITS*2-1:0] <= 0;
91+ dividend_gen[BITS*2*2-1:BITS*2] <= 0;
92+ end
93+ else begin
94+ div_by_zero_gen[1] <= div_by_zero_gen[0];
95+ start_gen[1] <= start_gen[0];
96+ negative_quotient_gen[1] <= negative_quotient_gen[0];
97+ divisor_gen[BITS*2*2-1:BITS*2] <= divisor_gen[BITS*2-1:0] >> 1;
98+ if ( dividend_gen[BITS*2-1:0] >= divisor_gen[BITS*2-1:0]) begin
99+ quotient_gen[BITS*2-1:0] <= 1 << STAGES - 2;
100+ dividend_gen[BITS*2*2-1:BITS*2] <= dividend_gen[BITS*2-1:0] - divisor_gen[BITS*2-1:0];
101+ end
102+ else begin
103+ quotient_gen[BITS*2-1:0] <= 0;
104+ dividend_gen[BITS*2*2-1:BITS*2] <= dividend_gen[BITS*2-1:0];
105+ end
106+ end // else: !if(!rst_n)
107+ end // always @ (posedge clk)
108+
109+ generate
110+ genvar i;
111+ for (i = 1; i < STAGES - 2; i = i + 1) begin : pipeline
112+ always @ (posedge clk or negedge rst_n) begin
113+ if (!rst_n) begin
114+ div_by_zero_gen[i+1] <= 0;
115+ start_gen[i+1] <= 0;
116+ negative_quotient_gen[i+1] <= 0;
117+ divisor_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= 0;
118+ quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= 0;
119+ dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= 0;
120+ end
121+ else begin
122+ div_by_zero_gen[i+1] <= div_by_zero_gen[i];
123+ start_gen[i+1] <= start_gen[i];
124+ negative_quotient_gen[i+1] <= negative_quotient_gen[i];
125+ divisor_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= divisor_gen[BITS*2*(i+1)-1:BITS*2*i] >> 1;
126+ if (dividend_gen[BITS*2*(i+1)-1:BITS*2*i] >= divisor_gen[BITS*2*(i+1)-1:BITS*2*i]) begin
127+ quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= quotient_gen[BITS*2*i-1:BITS*2*(i-1)] | (1 << (STAGES-2-i));
128+ dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= dividend_gen[BITS*2*(i+1)-1:BITS*2*i] - divisor_gen[BITS*2*(i+1)-1:BITS*2*i];
129+ end
130+ else begin
131+ quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= quotient_gen[BITS*2*i-1:BITS*2*(i-1)];
132+ dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= dividend_gen[BITS*2*(i+1)-1:BITS*2*i];
133+ end
134+ end // else: !if(!rst_n)
135+ end // always @ (posedge clk or negedge rst_n)
136+ end // block: pipeline
137+ endgenerate
138+
139+ // last computation stage
140+ always @ (posedge clk or negedge rst_n) begin
141+ if (!rst_n) begin
142+ div_by_zero_gen[STAGES-1] <= 0;
143+ start_gen[STAGES-1] <= 0;
144+ negative_quotient_gen[STAGES-1] <= 0;
145+ quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= 0;
146+ end
147+ else begin
148+ div_by_zero_gen[STAGES-1] <= div_by_zero_gen[STAGES-2];
149+ start_gen[STAGES-1] <= start_gen[STAGES-2];
150+ negative_quotient_gen[STAGES-1] <= negative_quotient_gen[STAGES-2];
151+ if ( dividend_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] >= divisor_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] )
152+ quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= quotient_gen[BITS*2*(STAGES-2)-1:BITS*2*(STAGES-3)] | 1;
153+ else
154+ quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= quotient_gen[BITS*2*(STAGES-2)-1:BITS*2*(STAGES-3)];
155+ end // else: !if(!rst_n)
156+ end // always @ (posedge clk)
157+
158+ // sign conversion stage
159+ always @ (posedge clk or negedge rst_n) begin
160+ if (!rst_n) begin
161+ div_by_zero <= 0;
162+ data_valid <= 0;
163+ quotient <= 0;
164+ end
165+ else begin
166+ div_by_zero <= div_by_zero_gen[STAGES-1];
167+ data_valid <= start_gen[STAGES-1];
168+ quotient <= (negative_quotient_gen[STAGES-1]) ? ~quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] + 1 : quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)];
169+ end
170+ end
171+
172+endmodule
tests/syntax-tests/source/Verilog/LICENSE.mdnew file+205
@@ -0,0 +1,205 @@
1+The `div_pipelined.v` file has been added from https://github.com/seldridge/verilog under the following license:
2+
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tests/syntax-tests/source/Verilog/div_pipelined.vnew file+172
@@ -0,0 +1,172 @@
1+// Copyright 2018 Schuyler Eldridge
2+//
3+// Licensed under the Apache License, Version 2.0 (the "License");
4+// you may not use this file except in compliance with the License.
5+// You may obtain a copy of the License at
6+//
7+// http://www.apache.org/licenses/LICENSE-2.0
8+//
9+// Unless required by applicable law or agreed to in writing, software
10+// distributed under the License is distributed on an "AS IS" BASIS,
11+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+// See the License for the specific language governing permissions and
13+// limitations under the License.
14+
15+// Implements a fixed-point parameterized pipelined division
16+// operation. Outputs are expected to be on range [-1,1), techincally
17+// [-1,2^(BITS-1)-1/2^(BITS-1)]. There is no convergent rounding.
18+//
19+// [TODO] Implement optional convergent rounding and some form of
20+// variable output binary point placement. There are arguments in
21+// these changes that make sense (specifically, adding an additional
22+// bit results in a gain of one value when all the other 2^6 values
23+// greater than 1 aren't used). Other improvements that are needed: 1)
24+// quotient_gen is getting smaller by one bit in every stage, it would
25+// make more sense to generate this as such, 2) there's some weird
26+// initial behavior after rst_n is deasserted, you get weird output on
27+// the quotient line for a number of cycles.
28+//
29+// [TODO] This doesn't exactly behave as expected if you specify
30+// different BITS and STAGES parameters (which for a functional
31+// module, should be implemented). Note, that this technically works,
32+// but needs more investigation to fully understand its properties.
33+
34+`timescale 1ns / 1ps
35+module div_pipelined
36+ (
37+ input clk,
38+ input rst_n,
39+ input start,
40+ input [BITS-1:0] dividend,
41+ input [BITS-1:0] divisor,
42+ output reg data_valid,
43+ output reg div_by_zero,
44+ output reg [STAGES-1:0] quotient
45+ // output reg [7:0] quotient_correct
46+ );
47+
48+ // WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
49+ // LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
50+ // OVERWRITTEN!
51+ parameter
52+ BITS = 8,
53+ STAGES = BITS;
54+
55+ // y = a/bQ
56+
57+ reg [STAGES-1:0] start_gen, negative_quotient_gen, div_by_zero_gen;
58+ reg [BITS*2*(STAGES-1)-1:0] dividend_gen, divisor_gen, quotient_gen;
59+ wire [BITS-1:0] pad_dividend;
60+ wire [BITS-2:0] pad_divisor;
61+
62+ assign pad_dividend = 0;
63+ assign pad_divisor = 0;
64+
65+ // sign conversion stage
66+ always @ (posedge clk or negedge rst_n)
67+ begin
68+ if (!rst_n) begin
69+ div_by_zero_gen[0] <= 0;
70+ start_gen[0] <=0;
71+ negative_quotient_gen[0] <= 0;
72+ dividend_gen[BITS*2-1:0] <= 0;
73+ divisor_gen[BITS*2-1:0] <= 0; end
74+ else begin
75+ div_by_zero_gen[0] <= (divisor == 0);
76+ start_gen[0] <= start;
77+ negative_quotient_gen[0] <= dividend[BITS-1] ^ divisor[BITS-1];
78+ dividend_gen[BITS*2-1:0] <= (dividend[BITS-1]) ? ~{dividend,pad_dividend} + 1 : {dividend,pad_dividend};
79+ divisor_gen[BITS*2-1:0] <= (divisor [BITS-1]) ? ~{1'b1,divisor, pad_divisor} + 1 : {1'b0,divisor, pad_divisor};
80+ end
81+ end
82+
83+ // first computation stage
84+ always @ (posedge clk or negedge rst_n) begin
85+ if (!rst_n) begin
86+ div_by_zero_gen[1] <= 0;
87+ start_gen[1] <= 0;
88+ negative_quotient_gen[1] <= 0;
89+ divisor_gen[BITS*2*2-1:BITS*2] <= 0;
90+ quotient_gen[BITS*2-1:0] <= 0;
91+ dividend_gen[BITS*2*2-1:BITS*2] <= 0;
92+ end
93+ else begin
94+ div_by_zero_gen[1] <= div_by_zero_gen[0];
95+ start_gen[1] <= start_gen[0];
96+ negative_quotient_gen[1] <= negative_quotient_gen[0];
97+ divisor_gen[BITS*2*2-1:BITS*2] <= divisor_gen[BITS*2-1:0] >> 1;
98+ if ( dividend_gen[BITS*2-1:0] >= divisor_gen[BITS*2-1:0]) begin
99+ quotient_gen[BITS*2-1:0] <= 1 << STAGES - 2;
100+ dividend_gen[BITS*2*2-1:BITS*2] <= dividend_gen[BITS*2-1:0] - divisor_gen[BITS*2-1:0];
101+ end
102+ else begin
103+ quotient_gen[BITS*2-1:0] <= 0;
104+ dividend_gen[BITS*2*2-1:BITS*2] <= dividend_gen[BITS*2-1:0];
105+ end
106+ end // else: !if(!rst_n)
107+ end // always @ (posedge clk)
108+
109+ generate
110+ genvar i;
111+ for (i = 1; i < STAGES - 2; i = i + 1) begin : pipeline
112+ always @ (posedge clk or negedge rst_n) begin
113+ if (!rst_n) begin
114+ div_by_zero_gen[i+1] <= 0;
115+ start_gen[i+1] <= 0;
116+ negative_quotient_gen[i+1] <= 0;
117+ divisor_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= 0;
118+ quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= 0;
119+ dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= 0;
120+ end
121+ else begin
122+ div_by_zero_gen[i+1] <= div_by_zero_gen[i];
123+ start_gen[i+1] <= start_gen[i];
124+ negative_quotient_gen[i+1] <= negative_quotient_gen[i];
125+ divisor_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= divisor_gen[BITS*2*(i+1)-1:BITS*2*i] >> 1;
126+ if (dividend_gen[BITS*2*(i+1)-1:BITS*2*i] >= divisor_gen[BITS*2*(i+1)-1:BITS*2*i]) begin
127+ quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= quotient_gen[BITS*2*i-1:BITS*2*(i-1)] | (1 << (STAGES-2-i));
128+ dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= dividend_gen[BITS*2*(i+1)-1:BITS*2*i] - divisor_gen[BITS*2*(i+1)-1:BITS*2*i];
129+ end
130+ else begin
131+ quotient_gen[BITS*2*(i+1)-1:BITS*2*i] <= quotient_gen[BITS*2*i-1:BITS*2*(i-1)];
132+ dividend_gen[BITS*2*(i+2)-1:BITS*2*(i+1)] <= dividend_gen[BITS*2*(i+1)-1:BITS*2*i];
133+ end
134+ end // else: !if(!rst_n)
135+ end // always @ (posedge clk or negedge rst_n)
136+ end // block: pipeline
137+ endgenerate
138+
139+ // last computation stage
140+ always @ (posedge clk or negedge rst_n) begin
141+ if (!rst_n) begin
142+ div_by_zero_gen[STAGES-1] <= 0;
143+ start_gen[STAGES-1] <= 0;
144+ negative_quotient_gen[STAGES-1] <= 0;
145+ quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= 0;
146+ end
147+ else begin
148+ div_by_zero_gen[STAGES-1] <= div_by_zero_gen[STAGES-2];
149+ start_gen[STAGES-1] <= start_gen[STAGES-2];
150+ negative_quotient_gen[STAGES-1] <= negative_quotient_gen[STAGES-2];
151+ if ( dividend_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] >= divisor_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] )
152+ quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= quotient_gen[BITS*2*(STAGES-2)-1:BITS*2*(STAGES-3)] | 1;
153+ else
154+ quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] <= quotient_gen[BITS*2*(STAGES-2)-1:BITS*2*(STAGES-3)];
155+ end // else: !if(!rst_n)
156+ end // always @ (posedge clk)
157+
158+ // sign conversion stage
159+ always @ (posedge clk or negedge rst_n) begin
160+ if (!rst_n) begin
161+ div_by_zero <= 0;
162+ data_valid <= 0;
163+ quotient <= 0;
164+ end
165+ else begin
166+ div_by_zero <= div_by_zero_gen[STAGES-1];
167+ data_valid <= start_gen[STAGES-1];
168+ quotient <= (negative_quotient_gen[STAGES-1]) ? ~quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)] + 1 : quotient_gen[BITS*2*(STAGES-1)-1:BITS*2*(STAGES-2)];
169+ end
170+ end
171+
172+endmodule