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Use one fewer variable for PortIn constraints
commit39eb4c6bc82897fc476b52839e766b51f371b3c6 authorEvan Czaplicki <info@elm-lang.org> dateSun 5 Jan 2014, 07:54 (13 years ago) parent6eb84d8
1 file changed+2−3
compiler/Type/Constrain/Expression.hs+2−3
compiler/Type/Constrain/Expression.hs+2−3
@@ -147,11 +147,10 @@ constrain env (L span expr) tipe =
147147 (c1 /\ c))
148148
149149 PortIn _ _ tt handler ->
150− exists $ \t1 ->
151− exists $ \t2 ->
150+ exists $ \tIncoming ->
152151 exists $ \tHandler -> do
153152 cHandler <- constrain env handler tHandler
154− return $ and [ cHandler, tHandler === (t1 ==> t2), tt === t2 ]
153+ return $ and [ cHandler, tHandler === (tIncoming ==> tt) ]
155154
156155 PortOut _ _ signal ->
157156 constrain env signal tipe