mirror of
https://github.com/ilyakooo0/Idris-dev.git
synced 2024-11-15 11:56:18 +03:00
5ea6aa0520
The changes are as follows: + `print` is for putting showable things to STDOUT. + `printLn` is for putting showable things to STDOUT with a new line + `putCharLn` for putting a single character to STDOUT, with a new line. Effects has been updated accordingly.
95 lines
2.8 KiB
Idris
95 lines
2.8 KiB
Idris
module main
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data Bit : Nat -> Type where
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b0 : Bit 0
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b1 : Bit 1
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instance Show (Bit n) where
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show b0 = "0"
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show b1 = "1"
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infixl 5 #
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data Binary : (width : Nat) -> (value : Nat) -> Type where
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zero : Binary Z Z
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(#) : Binary w v -> Bit bit -> Binary (S w) (bit + 2 * v)
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instance Show (Binary w k) where
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show zero = ""
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show (bin # bit) = show bin ++ show bit
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pattern syntax bitpair [x] [y] = (_ ** (_ ** (x, y, _)))
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term syntax bitpair [x] [y] = (_ ** (_ ** (x, y, Refl)))
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addBit : Bit x -> Bit y -> Bit c ->
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(bx ** (by ** (Bit bx, Bit by, c + x + y = by + 2 * bx)))
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addBit b0 b0 b0 = bitpair b0 b0
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addBit b0 b0 b1 = bitpair b0 b1
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addBit b0 b1 b0 = bitpair b0 b1
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addBit b0 b1 b1 = bitpair b1 b0
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addBit b1 b0 b0 = bitpair b0 b1
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addBit b1 b0 b1 = bitpair b1 b0
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addBit b1 b1 b0 = bitpair b1 b0
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addBit b1 b1 b1 = bitpair b1 b1
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adc : Binary w x -> Binary w y -> Bit c -> Binary (S w) (c + x + y)
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adc zero zero carry ?= zero # carry
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adc (numx # bx) (numy # by) carry
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?= let (bitpair carry0 lsb) = addBit bx by carry in
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adc numx numy carry0 # lsb
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main : IO ()
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main = do let n1 = zero # b1 # b0 # b1 # b0
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let n2 = zero # b1 # b1 # b1 # b0
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printLn (adc n1 n2 b0)
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---------- Proofs ----------
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-- There is almost certainly an easier proof. I don't care, for now :)
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main.adc_lemma_2 = proof {
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intro c,w,v,bit0,num0;
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intro b0,v1,bit1,num1,b1;
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intro bc,x,x1,bx,bx1,prf;
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intro;
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rewrite sym (plusZeroRightNeutral v);
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rewrite sym (plusZeroRightNeutral v1);
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rewrite sym (plusAssociative (plus c (plus bit0 (plus v v))) bit1 (plus v1 v1));
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rewrite (plusAssociative c (plus bit0 (plus v v)) bit1);
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rewrite (plusAssociative bit0 (plus v v) bit1);
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rewrite sym (plusCommutative (plus v v) bit1);
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rewrite sym (plusAssociative c bit0 (plus bit1 (plus v v)));
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rewrite sym (plusAssociative (plus c bit0) bit1 (plus v v));
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rewrite sym prf;
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rewrite sym (plusZeroRightNeutral x);
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rewrite plusAssociative x1 (plus x x) (plus v v);
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rewrite plusAssociative x x (plus v v);
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rewrite sym (plusAssociative x v v);
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rewrite plusCommutative v (plus x v);
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rewrite sym (plusAssociative x v (plus x v));
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rewrite plusAssociative x1 (plus (plus x v) (plus x v)) (plus v1 v1);
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rewrite plusAssociative (plus x v) (plus x v) (plus v1 v1);
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rewrite plusAssociative x v (plus v1 v1);
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rewrite sym (plusAssociative v v1 v1);
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rewrite sym (plusAssociative x (plus v v1) v1);
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rewrite sym (plusAssociative x v v1);
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rewrite sym (plusCommutative (plus (plus x v) v1) v1);
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rewrite plusZeroRightNeutral (plus (plus x v) v1);
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rewrite sym (plusAssociative (plus x v) v1 (plus (plus (plus x v) v1) Z));
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trivial;
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}
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main.adc_lemma_1 = proof {
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intros;
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rewrite sym (plusZeroRightNeutral c) ;
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trivial;
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}
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