Merge pull request #132589 from trepetti/pyverilog

python3Packages.pyverilog: init at 1.3.0

pkgs/development/python-modules/pyverilog/default.nix

@@ -0,0 +1,46 @@
+{ lib
+, buildPythonPackage
+, fetchPypi
+, pythonOlder
+, jinja2
+, ply
+, verilog
+, pytest-pythonpath
+, pytestCheckHook
+}:
+
+buildPythonPackage rec {
+  pname = "pyverilog";
+  version = "1.3.0";
+
+  src = fetchPypi {
+    inherit pname version;
+    sha256 = "1a74k8r21swmfwvgv4c014y6nbcyl229fspxw89ygsgb0j83xnar";
+  };
+
+  disabled = pythonOlder "3.7";
+
+  patchPhase = ''
+    # The path to Icarus can still be overridden via an environment variable at runtime.
+    substituteInPlace pyverilog/vparser/preprocessor.py \
+      --replace "iverilog = 'iverilog'" "iverilog = '${verilog}/bin/iverilog'"
+  '';
+
+  propagatedBuildInputs = [
+    jinja2
+    ply
+    verilog
+  ];
+
+  checkInputs = [
+    pytest-pythonpath
+    pytestCheckHook
+  ];
+
+  meta = with lib; {
+    homepage = "https://github.com/PyHDI/Pyverilog";
+    description = "Python-based Hardware Design Processing Toolkit for Verilog HDL";
+    license = licenses.asl20;
+    maintainers = with maintainers; [ trepetti ];
+  };
+}

pkgs/top-level/python-packages.nix

@@ -7323,6 +7323,8 @@ in {
 
   pyvera = callPackage ../development/python-modules/pyvera { };
 
+  pyverilog = callPackage ../development/python-modules/pyverilog { };
+
   pyvesync = callPackage ../development/python-modules/pyvesync { };
 
   pyvex = callPackage ../development/python-modules/pyvex { };