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Merge pull request #107507 from LibreCybernetics/add-zen-info
lib.systems: update processor architecture info
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fb875dcf6f
@ -12,6 +12,12 @@ rec {
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broadwell = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
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skylake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
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skylake-avx512 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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cannonlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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icelake-client = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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icelake-server = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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cascadelake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
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# x86_64 AMD
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btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ];
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btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
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@ -21,6 +27,7 @@ rec {
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bdver4 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" "fma4" ];
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znver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ];
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znver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ];
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znver3 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "sse4a" "aes" "avx" "avx2" "fma" ];
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# other
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armv5te = [ ];
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armv6 = [ ];
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@ -41,15 +48,38 @@ rec {
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broadwell = [ "haswell" ] ++ inferiors.haswell;
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skylake = [ "broadwell" ] ++ inferiors.broadwell;
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skylake-avx512 = [ "skylake" ] ++ inferiors.skylake;
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# x86_64 AMD
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# TODO: fill this (need testing)
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btver1 = [ ];
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btver2 = [ ]; # TODO: fill this (need testing)
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bdver1 = [ ]; # TODO: fill this (need testing)
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bdver2 = [ ]; # TODO: fill this (need testing)
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bdver3 = [ ]; # TODO: fill this (need testing)
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bdver4 = [ ]; # TODO: fill this (need testing)
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znver1 = [ ]; # TODO: fill this (need testing)
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znver2 = [ ]; # TODO: fill this (need testing)
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btver2 = [ ];
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bdver1 = [ ];
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bdver2 = [ ];
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bdver3 = [ ];
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bdver4 = [ ];
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# Regarding `skylake` as inferior of `znver1`, there are reports of
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# successful usage by Gentoo users and Phoronix benchmarking of different
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# `-march` targets.
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#
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# The GCC documentation on extensions used and wikichip documentation
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# regarding supperted extensions on znver1 and skylake was used to create
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# this partial order.
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#
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# Note:
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#
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# - The succesors of `skylake` (`cannonlake`, `icelake`, etc) use `avx512`
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# which no current AMD Zen michroarch support.
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# - `znver1` uses `ABM`, `CLZERO`, `CX16`, `MWAITX`, and `SSE4A` which no
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# current Intel microarch support.
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#
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# https://www.phoronix.com/scan.php?page=article&item=amd-znver3-gcc11&num=1
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# https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
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# https://en.wikichip.org/wiki/amd/microarchitectures/zen
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# https://en.wikichip.org/wiki/intel/microarchitectures/skylake
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znver1 = [ "skylake" ] ++ inferiors.skylake;
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znver2 = [ "znver1" ] ++ inferiors.znver1;
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znver3 = [ "znver2" ] ++ inferiors.znver2;
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# other
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armv5te = [ ];
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armv6 = [ ];
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@ -76,10 +76,14 @@ let
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cannonlake = versionAtLeast ccVersion "8.0";
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icelake-client = versionAtLeast ccVersion "8.0";
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icelake-server = versionAtLeast ccVersion "8.0";
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cascadelake = versionAtLeast ccVersion "9.0";
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cooperlake = versionAtLeast ccVersion "10.0";
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tigerlake = versionAtLeast ccVersion "10.0";
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knm = versionAtLeast ccVersion "8.0";
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# AMD
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znver1 = versionAtLeast ccVersion "6.0";
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znver2 = versionAtLeast ccVersion "9.0";
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znver3 = versionAtLeast ccVersion "11.0";
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}.${arch} or true
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else if isClang then
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{ # Intel
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