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Fix hlint issues in streamly package

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This commit is contained in:
Harendra Kumar 2023-12-18 22:41:21 +05:30
parent 7f711f7c93
commit 86ad39afeb
3 changed files with 8 additions and 5 deletions
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3
.hlint.ignore
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@ -2,6 +2,9 @@ core/src/Streamly/Internal/Data/Stream/StreamK/Type.hs
core/src/Streamly/Internal/Data/Pipe/Type.hs
core/src/Streamly/Internal/Unicode/Stream.hs
src/Streamly/Internal/Data/SmallArray/Type.hs
src/Streamly/Internal/Data/Stream/IsStream/Eliminate.hs
src/Streamly/Internal/Data/Stream/Serial.hs
src/Streamly/Internal/Data/Stream/Zip.hs
test/Streamly/Test/Data/Array.hs
test/Streamly/Test/Data/Parser.hs
test/Streamly/Test/Data/ParserK.hs

4
src/Streamly/Internal/Data/Stream/Concurrent.hs
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@ -646,8 +646,8 @@ parConcatIterate modifier f input =
where
iterateStream channel stream =
parConcatMapChanKGeneric modifier channel (generate channel) stream
iterateStream channel =
parConcatMapChanKGeneric modifier channel (generate channel)
generate channel x =
-- XXX The channel q should be FIFO for DFS, otherwise it is BFS

6
src/Streamly/Internal/Unicode/Char.hs
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@ -227,13 +227,13 @@ partialComposeD (Stream step state) = Stream step' (ComposeNone state)
Stop -> Skip $ YieldList rbuf ComposeStop
{-# INLINE initHangul #-}
initHangul c st = ComposeJamo (Hangul c) st
initHangul c = ComposeJamo (Hangul c)
{-# INLINE initJamo #-}
initJamo c st = ComposeJamo (Jamo c) st
initJamo c = ComposeJamo (Jamo c)
{-# INLINE initReg #-}
initReg !c st = ComposeReg 0 [c] st
initReg !c = ComposeReg 0 [c]
{-# INLINE composeNone #-}
composeNone ch st