Nicolas Boulenguez 26ced15b31 Remove gensym, inc and or from step files. ... * Move `gensym` and `inc` from step files to `lib/trivial.mal`. * Move `or` from step files to `lib/test_cascade.mal`. Shorten it because `(first ())` returns `nil` * Update process and tests accordingly (not the figures yet).		2019-07-09 14:05:29 +02:00
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.gitignore	Add VHDL implementation	2016-05-05 14:50:12 -04:00
core.vhdl	vhdl: Fix time-ms: Return milliseconds since last midnight UTC to fit in 32-bit integer	2017-11-02 09:49:21 +00:00
Dockerfile	vhdl: Update Dockerfile, add Travis-CI build	2016-05-05 16:06:28 -04:00
env.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
Makefile	Convert to loccount based stats calculation.	2019-03-20 23:34:21 -05:00
pkg_readline.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
printer.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
reader.vhdl	Error on unterminated strings.	2019-01-25 16:16:06 -06:00
run	Refactor to use run scripts, remove *_RUNSTEP	2016-05-18 22:29:18 -07:00
run_vhdl.sh	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step0_repl.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step1_read_print.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step2_eval.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step3_env.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step4_if_fn_do.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step5_tco.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step6_file.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step7_quote.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00
step8_macros.vhdl	Remove gensym, inc and or from step files.	2019-07-09 14:05:29 +02:00
step9_try.vhdl	Remove gensym, inc and or from step files.	2019-07-09 14:05:29 +02:00
stepA_mal.vhdl	Remove gensym, inc and or from step files.	2019-07-09 14:05:29 +02:00
types.vhdl	Add VHDL implementation	2016-05-05 14:50:12 -04:00