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46 lines
948 B
VHDL
46 lines
948 B
VHDL
entity step0_repl is
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end entity step0_repl;
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library STD;
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use STD.textio.all;
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library WORK;
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use WORK.pkg_readline.all;
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architecture test of step0_repl is
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function mal_READ(str: in string) return string is
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begin
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return str;
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end function mal_READ;
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function EVAL(ast: in string; env: in string) return string is
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begin
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return ast;
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end function EVAL;
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function mal_PRINT(exp: in string) return string is
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begin
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return exp;
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end function mal_PRINT;
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function REP(str: in string) return string is
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begin
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return mal_PRINT(EVAL(mal_READ(str), ""));
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end function REP;
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procedure repl is
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variable is_eof: boolean;
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variable input_line: line;
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begin
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loop
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mal_readline("user> ", is_eof, input_line);
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exit when is_eof;
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next when input_line'length = 0;
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mal_printline(REP(input_line.all));
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end loop;
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mal_printline("");
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end procedure repl;
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begin
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repl;
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end architecture test;
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