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getting closer to correct evaluate

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This commit is contained in:
Amadeo Bellotti 2024-01-23 14:40:52 -05:00
parent 1fe9aab915
commit 35a41c0a82
5 changed files with 189 additions and 98 deletions
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2
memory/evaluate.hex
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@ -5,5 +5,5 @@
0000000050000006
0300000000000003
0200000010000007
0200000040000007
0200000040000008
0300000000000001

4
testbenches/execute_tb.v
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@ -6,8 +6,8 @@ module execute_tb();
//Test Parameters
//parameter MEM_INIT_FILE = "./memory/slot_tb.hex";
//parameter MEM_INIT_FILE = "./memory/inc_slot.hex";
parameter MEM_INIT_FILE = "./memory/evaluate2.hex";
parameter MEM_INIT_FILE = "./memory/inc_slot.hex";
//parameter MEM_INIT_FILE = "./memory/evaluate.hex";
//parameter MEM_INIT_FILE = "./memory/constant_tb.hex";
//parameter MEM_INIT_FILE = "./memory/nested_increment.hex";

145
verilog/execute.v
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@ -25,6 +25,7 @@ module execute (
input clk, rst;
output reg [7:0] error;
reg [7:0] debug_sig;
// Interface with memory traversal
input execute_start; // wire to begin execution (mux_conroller from traversal)
reg execute_start_ff;
@ -51,7 +52,6 @@ module execute (
//Registers to treat opcodes as "Functions"
reg [`noun_width - 1:0] a, opcode, b, c, d;
reg [3:0] func_tag;
reg [`noun_width - 1:0] func_addr;
reg [3:0] func_return_exec_func;
reg [3:0] func_return_state;
@ -152,6 +152,7 @@ module execute (
parameter EXE_INIT_INIT = 4'h0,
EXE_INIT_READ_TEL = 4'h1,
EXE_INIT_DECODE = 4'h2,
EXE_INIT_WRIT_TEL = 4'h3,
EXE_INIT_FINISHED = 4'hF;
//Stacking States
@ -172,7 +173,7 @@ module execute (
end
always @(posedge clk or negedge rst) begin
if (!rst) begin
if (!rst || (execute_start && !execute_start_ff)) begin
exec_func <= EXE_FUNC_INIT;
state <= EXE_INIT_INIT;
trav_B <= `NIL;
@ -183,20 +184,9 @@ module execute (
stack_mem_tag_1 <= 0;
stack_mem_tag_2 <= 0;
write_data <= 0;
func_tag <= 0;
mem_execute<=0;
//end else if (execute_start && !execute_start_ff) begin
//exec_func <= EXE_FUNC_INIT;
//state <= EXE_INIT_INIT;
//trav_B <= `NIL;
//is_finished_reg <= 0;
//read_data_reg <= 0;
//execute_return_sys_func <= 0;
//execute_return_state <= 0;
//stack_mem_tag_1 <= 0;
//stack_mem_tag_2 <= 0;
//write_data <= 0;
//func_tag <= 0;
debug_sig <= 0;
address <=0;
end else if (execute_start) begin
case (exec_func)
EXE_FUNC_INIT: begin
@ -215,8 +205,9 @@ module execute (
execute_address_reg <= execute_address;
trav_P <= execute_address;
b<= 16'hDEAD;
a <= execute_data[`hed_start:`hed_end];
func_tag[0] <= execute_data[`tag_end+1];
address <= execute_data[`tel_start:`tel_end];
mem_func <= `GET_CONTENTS;
@ -233,14 +224,49 @@ module execute (
EXE_INIT_READ_TEL: begin
if (mem_ready) begin
mem_data <= read_data;
mem_tag <= read_data[`tag_start:`tag_end]; // read first 4 bits and store into tag for easier access
// if data is [cell NIL] read hed
if(read_data[`tel_start:`tel_end] ==`NIL && read_data[`tel_tag] == `ATOM) begin
if(read_data[`hed_tag] == `CELL) begin
debug_sig <= 7;
address <= read_data[`hed_start:`hed_end];
mem_func <= `GET_CONTENTS;
mem_execute <= 1;
state <= EXE_INIT_WRIT_TEL;
end else begin
error <= `ERROR_TEL_NOT_CELL;
exec_func <= EXE_FUNC_ERROR;
state <= EXE_ERROR_INIT;
end
opcode <= read_data[`hed_start:`hed_end];
b <= read_data[`tel_start:`tel_end];
func_tag[1] <= execute_data[`tag_end];
end else begin
mem_data <= read_data;
mem_tag <= read_data[`tag_start:`tag_end]; // read first 4 bits and store into tag for easier access
state <= EXE_INIT_DECODE;
opcode <= read_data[`hed_start:`hed_end];
b <= read_data[`tel_start:`tel_end];
state <= EXE_INIT_DECODE;
end
end else begin
mem_func <= 0;
mem_execute <= 0;
end
end
EXE_INIT_WRIT_TEL: begin
if (mem_ready) begin
debug_sig <= 22;
write_addr_reg <= execute_address;
mem_execute <= 1;
write_data <= {execute_data[`tag_start:`tag_end],
execute_data[`hed_start:`hed_end],
18'b0,address};//data[`tel_start:`tel_end]};
address <= execute_address;
mem_func <= `SET_CONTENTS;
mem_execute <= 1;
state <= EXE_INIT_READ_TEL;
end else begin
mem_func <= 0;
mem_execute <= 0;
@ -295,7 +321,7 @@ module execute (
state <= EXE_STACK_INIT;
end else begin
// Throw error invalid increment formulation
error <= `ERROR_INVALID_B;
error <= `ERROR_INVALID_B_CELL;
exec_func <= EXE_FUNC_ERROR;
state <= EXE_ERROR_INIT;
end
@ -310,7 +336,8 @@ module execute (
state <= EXE_STACK_INIT;
end else begin
// Throw error invalid increment formulation
error <= `ERROR_INVALID_B;
debug_sig <= 16;
error <= `ERROR_INVALID_B_INCR;
exec_func <= EXE_FUNC_ERROR;
state <= EXE_ERROR_INIT;
end
@ -384,7 +411,8 @@ module execute (
EXE_SLOT_INIT: begin
b <= (read_data[`tel_start:`tel_end]<<1) | 1;
address <= execute_data[`hed_start:`hed_end]; // Read subject
subject <= {execute_data[`hed_tag],execute_data[`hed_start:`hed_end]};
subject <= execute_data[`hed_start:`hed_end];
subject_tag <= execute_data[`hed_tag];
mem_reg <= execute_data;
state <= EXE_SLOT_PREP;
mem_execute <= 1;
@ -410,9 +438,9 @@ module execute (
mem_execute <= 1;
write_data <= {
6'b000000,
subject[`noun_width],
subject_tag,
1'b1,
subject[`noun_width-1:0],
subject,
`NIL};
//1'b0,
//read_data[62:0]};
@ -428,7 +456,8 @@ module execute (
if (b[`noun_width-1] == 0) begin
if(read_data[`hed_tag] == `CELL) begin
address <= read_data[`hed_start:`hed_end];
subject <= {read_data[`hed_tag],read_data[`hed_start:`hed_end]};
subject <= read_data[`hed_start:`hed_end];
subject_tag <= read_data[`hed_tag];
mem_func <= `GET_CONTENTS;
mem_execute <= 1;
state <= EXE_SLOT_CHECK;
@ -441,7 +470,7 @@ module execute (
write_data <= {
6'b000000,
read_data[`hed_tag],
1'b0,
1'b1,
read_data[`hed_start:`hed_end],
`NIL};
//28'h0000};
@ -454,7 +483,8 @@ module execute (
end else begin
if(read_data[`tel_tag] == `CELL) begin
address <= read_data[`tel_start:`tel_end];
subject <= {read_data[`tel_tag],read_data[`tel_start:`tel_end]};
subject <= read_data[`tel_start:`tel_end];
subject_tag <= read_data[`tel_tag];
mem_func <= `GET_CONTENTS;
mem_execute <= 1;
state <= EXE_SLOT_CHECK;
@ -467,7 +497,7 @@ module execute (
write_data <= {
6'b000000,
read_data[`tel_tag],
1'b0,
1'b1,
read_data[`tel_start:`tel_end],
`NIL};
//28'h0000};
@ -661,8 +691,9 @@ module execute (
address <= func_addr;
mem_func <= `SET_CONTENTS;
mem_execute <= 1;
write_data <= {8'b00000011,
27'h0, read_data[`hed_tag],
write_data <= {6'b000000,
2'b11,
27'h0, read_data[`hed_tag],
`NIL};
state <= EXE_CELL_WRITE_WAIT;
end else begin
@ -705,9 +736,13 @@ module execute (
EXE_INCR_A: begin
if (mem_ready) begin
if (read_data[`hed_tag] == `CELL) begin
error <= `ERROR_INVALID_B;
exec_func <= EXE_FUNC_ERROR;
state <= EXE_ERROR_INIT;
debug_sig <= 12;
stack_P <= trav_P;
exec_func <= EXE_FUNC_STACK;
state <= EXE_STACK_INIT;
//error <= `ERROR_INVALID_B_INCR;
//exec_func <= EXE_FUNC_ERROR;
//state <= EXE_ERROR_INIT;
end else begin
address <= func_addr;
write_addr_reg <= func_addr;
@ -774,7 +809,7 @@ module execute (
EXE_FUNC_STACK: begin
case (state)
EXE_STACK_INIT: begin
EXE_STACK_INIT: begin // D0
address <= stack_P;
trav_P <= stack_P;
mem_func <= `GET_CONTENTS;
@ -782,8 +817,9 @@ module execute (
state <= EXE_STACK_READ_WAIT;
end
EXE_STACK_READ_WAIT: begin
EXE_STACK_READ_WAIT: begin // D1
if (mem_ready) begin
read_data_reg <= read_data;
stack_a <= read_data[`hed_start:`hed_end];
address <= read_data[`tel_start:`tel_end];
stack_P_tel <= read_data[`tel_start:`tel_end];
@ -799,22 +835,23 @@ module execute (
end
end
EXE_STACK_READ_WAIT_2: begin
EXE_STACK_READ_WAIT_2: begin //D2
if (mem_ready) begin
stack_b <= read_data[`tel_start:`tel_end];
stack_mem_tag_2 <= read_data[`tag_start:`tag_end];
stack_b <= read_data_reg[`tel_start:`tel_end];
stack_mem_tag_2 <= read_data_reg[`tag_start:`tag_end];
address <= stack_P;
write_data <= {
stack_mem_tag_1[7],
3'b000,
read_data[`tag_start-1],
read_data_reg[`tag_start-1],
stack_mem_tag_1[2],
read_data[`tag_start-3],
read_data_reg[`tag_start-3],
stack_mem_tag_1[0],
read_data[`hed_start:`hed_end],
read_data_reg[`hed_start:`hed_end],
trav_B
}; //Set data to visited tel and b in tel while swaping opcode and a
if(trav_B == `NIL) debug_sig <= 32;
mem_func <= `SET_CONTENTS;
mem_execute <= 1;
state <= EXE_STACK_WRITE_WAIT;
@ -824,7 +861,7 @@ module execute (
end
end
EXE_STACK_WRITE_WAIT: begin
EXE_STACK_WRITE_WAIT: begin //D3
if (mem_ready) begin
address <= stack_P_tel;
write_data <= {
@ -850,7 +887,7 @@ module execute (
end
end
EXE_STACK_CHECK_NEXT: begin
EXE_STACK_CHECK_NEXT: begin //D4
if (mem_ready) begin
address <= read_data[`tel_start:`tel_end];
mem_func <= `GET_CONTENTS;
@ -863,7 +900,7 @@ module execute (
end
end
EXE_STACK_CHECK_WAIT: begin
EXE_STACK_CHECK_WAIT: begin //D5
if (mem_ready) begin
if((read_data[`hed_start:`hed_end] < 0) || (read_data[`hed_start:`hed_end] > 11)) begin //If invalid opcode
error <= `ERROR_INVALID_OPCODE;
@ -873,10 +910,8 @@ module execute (
exec_func <= EXE_FUNC_SLOT;
state <= EXE_SLOT_INIT;
a <= stack_a;
func_tag[0] <= stack_mem_tag_1[1];
b <= read_data[`tel_start:`tel_end];
func_tag[1] <= read_data[`tag_end+1];
func_addr <= stack_P_tel;
trav_P <= stack_P_tel;
@ -887,10 +922,8 @@ module execute (
exec_func <= EXE_FUNC_CONSTANT;
state <= EXE_CONSTANT_INIT;
a <= stack_a;
func_tag[0] <= stack_mem_tag_1[1];
b <= read_data[`tel_start:`tel_end];
func_tag[1] <= read_data[`tag_end+1];
func_addr <= stack_P_tel;
trav_P <= stack_P_tel;
@ -898,6 +931,7 @@ module execute (
func_return_exec_func <= EXE_FUNC_STACK;
func_return_state <= EXE_STACK_POP;
end else begin
debug_sig<=33;
stack_P <= stack_P_tel;
state <= EXE_STACK_INIT;
end
@ -907,7 +941,7 @@ module execute (
end
end
EXE_STACK_POP: begin
EXE_STACK_POP: begin //D6
if (mem_ready) begin
trav_P <= trav_B;
address <= trav_P;
@ -920,10 +954,9 @@ module execute (
end
end
EXE_STACK_POP_READ: begin
EXE_STACK_POP_READ: begin //D7
if (mem_ready) begin
a <= read_data[`hed_start:`hed_end];
func_tag[0] <= read_data[`tag_end];
address <= trav_B;
mem_func <= `GET_CONTENTS;
@ -935,7 +968,7 @@ module execute (
end
end
EXE_STACK_POP_WAIT: begin
EXE_STACK_POP_WAIT: begin //D8
if (mem_ready) begin
opcode <= read_data[`hed_start:`hed_end];
trav_B <= read_data[`tel_start:`tel_end];
@ -996,7 +1029,7 @@ module execute (
end
end
EXE_STACK_POP_ERR: begin
EXE_STACK_POP_ERR: begin // D9
if (mem_ready) begin
$stop;
end else begin

9
verilog/execute.vh
View File

@ -25,10 +25,11 @@
// Error Definitions
`define ERROR_TEL_NOT_CELL 8'h01
`define ERROR_INVALID_OPCODE 8'h02
`define ERROR_INVALID_B 8'h03
`define ERROR_INVALID_SLOT 8'h04
`define ERROR_INVALID_SLOT_HED 8'h05
`define ERROR_INVALID_SLOT_TEL 8'h06
`define ERROR_INVALID_B_CELL 8'h03
`define ERROR_INVALID_B_INCR 8'h04
`define ERROR_INVALID_SLOT 8'h05
`define ERROR_INVALID_SLOT_HED 8'h06
`define ERROR_INVALID_SLOT_TEL 8'h07
`endif

127
verilog/mem_traversal.v
View File

@ -51,7 +51,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
output reg [`noun_tag_width - 1:0] noun_tag_gp;
// [[50 51] [2 [0 3] [1 [4 0 1]]]]
reg [0:0] debug_flag;
// Traversal Registers needed
reg [`noun_width - 1:0] trav_P;
@ -88,6 +87,7 @@ module mem_traversal(power, clk, rst, start_addr, execute,
SYS_EXECUTE_READ_TEL = 4'h2,
SYS_EXECUTE_WAIT = 4'h3,
SYS_EXECUTE_DECODE = 4'h4,
SYS_EXECUTE_READ_ADDR = 4'h5,
SYS_EXECUTE_ERROR = 4'hF;
always@(posedge clk or negedge rst) begin
@ -101,7 +101,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
mem_execute <= 0;
debug_sig <= 0;
mux_controller <= 0;
debug_flag <=0;
end
else if (execute) begin
@ -127,10 +126,14 @@ module mem_traversal(power, clk, rst, start_addr, execute,
state <= SYS_EXECUTE_READ_TEL;
end
else begin
address <= mem_data[`tel_start:`tel_end];
mem_func <= `GET_CONTENTS;
mem_execute <= 1;
execute_address <= mem_addr;
execute_data <= mem_data;
execute_tag <= mem_tag;
mux_controller <= 1;
debug_sig <= 3;
state <= SYS_EXECUTE_WAIT;
end
end
@ -138,9 +141,9 @@ module mem_traversal(power, clk, rst, start_addr, execute,
SYS_EXECUTE_READ_HED: begin
if(mem_ready) begin
if(read_data[`execute_bit]==1) begin
debug_flag <=1;
// If we need to execute the hed
$stop;
sys_func <= SYS_FUNC_TRAVERSE;
state <= SYS_TRAVERSE_INIT;
end
else begin
if (mem_data_gp[`tel_tag]==`CELL) begin
@ -154,10 +157,14 @@ module mem_traversal(power, clk, rst, start_addr, execute,
else begin
// if not executing hed and parent then pass data to
// the execute block
address <= mem_data_gp[`tel_start:`tel_end];
mem_func <= `GET_CONTENTS;
mem_execute <= 1;
execute_address <= mem_addr;
execute_data <= mem_data;
execute_tag <= mem_tag;
mux_controller <= 1;
debug_sig <= 2;
state <= SYS_EXECUTE_WAIT;
end
end
@ -173,37 +180,63 @@ module mem_traversal(power, clk, rst, start_addr, execute,
if(mem_ready) begin
if(read_data[`execute_bit]==1) begin
// If we need to execute the tel
$stop;
sys_func <= SYS_FUNC_TRAVERSE;
state <= SYS_TRAVERSE_INIT;
end
else begin
// if not executing hed and parent then pass data to
// the execute block
debug_sig <= 1;
if(trav_B != `NIL) mem_addr <= trav_B;
execute_address <= mem_addr;
execute_data <= mem_data;
execute_tag <= mem_tag;
execute_data <= {mem_tag,hed,tel};//read_data;
execute_tag <= mem_tag;//read_data[`tag_start:`tag_end];
//execute_data <= mem_data;
//execute_tag <= mem_tag;
mux_controller <= 1;
state <= SYS_EXECUTE_WAIT;
end
end
else begin
mem_func <= 0;
mem_execute <= 0;
end
//address <= mem_addr;
//mem_func <= `GET_CONTENTS;
//mem_execute <= 1;
//state <= SYS_EXECUTE_READ_ADDR;
end
end
else begin
mem_func <= 0;
mem_execute <= 0;
end
SYS_EXECUTE_WAIT: begin
if(execute_finished) begin
sys_func = execute_return_sys_func;
state = execute_return_state;
mux_controller <= 0;
end
end
end
SYS_EXECUTE_READ_ADDR: begin
if(mem_ready) begin
debug_sig <= 6;
if(trav_B != `NIL) mem_addr <= trav_B;
execute_address <= mem_addr;
execute_data <= {mem_tag,hed,tel};//read_data;
execute_tag <= mem_tag;//read_data[`tag_start:`tag_end];
mux_controller <= 1;
state <= SYS_EXECUTE_WAIT;
end else begin
mem_func <= 0;
mem_execute <= 0;
end
end
SYS_EXECUTE_ERROR: begin
state <= SYS_EXECUTE_ERROR;
is_finished_reg <= 1;
end
SYS_EXECUTE_WAIT: begin
if(execute_finished) begin
debug_sig <= 0;
sys_func = execute_return_sys_func;
state = execute_return_state;
mux_controller <= 0;
end
end
SYS_EXECUTE_ERROR: begin
state <= SYS_EXECUTE_ERROR;
is_finished_reg <= 1;
end
endcase
@ -212,7 +245,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
SYS_FUNC_READ: begin
case(state)
SYS_READ_INIT: begin
debug_flag <=0;
if(mem_addr == 1023) begin // mem_addr is only max when you reach the end and use trav_b's inital value
is_finished_reg <= 1;
end
@ -234,10 +266,16 @@ module mem_traversal(power, clk, rst, start_addr, execute,
hed <= read_data[`hed_start:`hed_end];
tel <= read_data[`tel_start:`tel_end];
//if tel is nil do soemthing?
// If cell is marked for execution
if(read_data[`execute_bit] == 1) begin
sys_func <= SYS_FUNC_EXECUTE;
state <= SYS_EXECUTE_INIT;
if (read_data[`tel_start:`tel_end] == `NIL) begin
sys_func <= SYS_FUNC_TRAVERSE;
state <= SYS_TRAVERSE_INIT;
end else begin
sys_func <= SYS_FUNC_EXECUTE;
state <= SYS_EXECUTE_INIT;
end
end
else begin
sys_func <= SYS_FUNC_TRAVERSE;
@ -258,7 +296,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
SYS_FUNC_WRITE: begin
case(state)
SYS_WRITE_INIT: begin
debug_flag <=0;
address <= mem_addr;
write_data <= {mem_tag, hed, tel};
mem_func <= `SET_CONTENTS;
@ -285,7 +322,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
SYS_FUNC_TRAVERSE: begin
case(state)
SYS_TRAVERSE_INIT: begin
debug_flag <=1;
case(mem_tag[1:0])
`CELL_CELL: begin
if(mem_tag[3:2] == 2'b00) begin // if the hed cell hasn't been visited we push into it
@ -323,8 +359,13 @@ module mem_traversal(power, clk, rst, start_addr, execute,
end
else if(mem_tag[3:2] == 2'b11) begin // if both were visited
// Set the command after write to pop
write_return_sys_func <= SYS_FUNC_TRAVERSE;
write_return_state <= SYS_TRAVERSE_POP;
if(mem_tag[7] == 1) begin // If we still need to execute
write_return_sys_func <= SYS_FUNC_EXECUTE;
write_return_state <= SYS_EXECUTE_INIT;
end else begin
write_return_sys_func <= SYS_FUNC_TRAVERSE;
write_return_state <= SYS_TRAVERSE_POP;
end
mem_tag[3:2] <= 2'b00;
@ -346,6 +387,7 @@ module mem_traversal(power, clk, rst, start_addr, execute,
`ATOM_CELL: begin
if(mem_tag[2] == 1'b0) begin // if both were visited
debug_sig <= 1;
// Set the command after write to traverse the tel
write_return_sys_func <= SYS_FUNC_TRAVERSE;
@ -364,9 +406,17 @@ module mem_traversal(power, clk, rst, start_addr, execute,
state <= SYS_WRITE_INIT;
end
else begin
debug_sig <= 2;
// Set the command after write to pop
write_return_sys_func <= SYS_FUNC_TRAVERSE;
write_return_state <= SYS_TRAVERSE_POP;
if(mem_tag[7] == 1) begin // If we still need to execute
write_return_sys_func <= SYS_FUNC_EXECUTE;
write_return_state <= SYS_EXECUTE_INIT;
end else begin
write_return_sys_func <= SYS_FUNC_TRAVERSE;
write_return_state <= SYS_TRAVERSE_POP;
end
//write_return_sys_func <= SYS_FUNC_TRAVERSE;
//write_return_state <= SYS_TRAVERSE_POP;
mem_tag[3:2] <= 2'b00;
@ -400,8 +450,15 @@ module mem_traversal(power, clk, rst, start_addr, execute,
end
else begin
// Set the command after write to pop
write_return_sys_func <= SYS_FUNC_TRAVERSE;
write_return_state <= SYS_TRAVERSE_POP;
if(mem_tag[7] == 1) begin // If we still need to execute
write_return_sys_func <= SYS_FUNC_EXECUTE;
write_return_state <= SYS_EXECUTE_INIT;
end else begin
write_return_sys_func <= SYS_FUNC_TRAVERSE;
write_return_state <= SYS_TRAVERSE_POP;
end
//write_return_sys_func <= SYS_FUNC_TRAVERSE;
//write_return_state <= SYS_TRAVERSE_POP;
mem_tag[3:2] <= 2'b00;