mirror of
https://github.com/mopfel-winrux/NockPU.git
synced 2024-10-06 01:37:16 +03:00
getting closer to correct evaluate
This commit is contained in:
parent
1fe9aab915
commit
35a41c0a82
@ -5,5 +5,5 @@
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0000000050000006
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0300000000000003
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0200000010000007
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0200000040000007
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0200000040000008
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0300000000000001
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@ -6,8 +6,8 @@ module execute_tb();
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//Test Parameters
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//parameter MEM_INIT_FILE = "./memory/slot_tb.hex";
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//parameter MEM_INIT_FILE = "./memory/inc_slot.hex";
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parameter MEM_INIT_FILE = "./memory/evaluate2.hex";
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parameter MEM_INIT_FILE = "./memory/inc_slot.hex";
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//parameter MEM_INIT_FILE = "./memory/evaluate.hex";
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//parameter MEM_INIT_FILE = "./memory/constant_tb.hex";
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//parameter MEM_INIT_FILE = "./memory/nested_increment.hex";
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@ -25,6 +25,7 @@ module execute (
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input clk, rst;
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output reg [7:0] error;
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reg [7:0] debug_sig;
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// Interface with memory traversal
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input execute_start; // wire to begin execution (mux_conroller from traversal)
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reg execute_start_ff;
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@ -51,7 +52,6 @@ module execute (
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//Registers to treat opcodes as "Functions"
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reg [`noun_width - 1:0] a, opcode, b, c, d;
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reg [3:0] func_tag;
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reg [`noun_width - 1:0] func_addr;
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reg [3:0] func_return_exec_func;
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reg [3:0] func_return_state;
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@ -152,6 +152,7 @@ module execute (
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parameter EXE_INIT_INIT = 4'h0,
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EXE_INIT_READ_TEL = 4'h1,
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EXE_INIT_DECODE = 4'h2,
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EXE_INIT_WRIT_TEL = 4'h3,
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EXE_INIT_FINISHED = 4'hF;
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//Stacking States
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@ -172,7 +173,7 @@ module execute (
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end
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always @(posedge clk or negedge rst) begin
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if (!rst) begin
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if (!rst || (execute_start && !execute_start_ff)) begin
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exec_func <= EXE_FUNC_INIT;
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state <= EXE_INIT_INIT;
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trav_B <= `NIL;
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@ -183,20 +184,9 @@ module execute (
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stack_mem_tag_1 <= 0;
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stack_mem_tag_2 <= 0;
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write_data <= 0;
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func_tag <= 0;
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mem_execute<=0;
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//end else if (execute_start && !execute_start_ff) begin
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//exec_func <= EXE_FUNC_INIT;
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//state <= EXE_INIT_INIT;
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//trav_B <= `NIL;
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//is_finished_reg <= 0;
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//read_data_reg <= 0;
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//execute_return_sys_func <= 0;
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//execute_return_state <= 0;
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//stack_mem_tag_1 <= 0;
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//stack_mem_tag_2 <= 0;
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//write_data <= 0;
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//func_tag <= 0;
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debug_sig <= 0;
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address <=0;
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end else if (execute_start) begin
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case (exec_func)
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EXE_FUNC_INIT: begin
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@ -215,8 +205,9 @@ module execute (
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execute_address_reg <= execute_address;
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trav_P <= execute_address;
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b<= 16'hDEAD;
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a <= execute_data[`hed_start:`hed_end];
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func_tag[0] <= execute_data[`tag_end+1];
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address <= execute_data[`tel_start:`tel_end];
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mem_func <= `GET_CONTENTS;
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@ -233,14 +224,49 @@ module execute (
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EXE_INIT_READ_TEL: begin
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if (mem_ready) begin
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// if data is [cell NIL] read hed
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if(read_data[`tel_start:`tel_end] ==`NIL && read_data[`tel_tag] == `ATOM) begin
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if(read_data[`hed_tag] == `CELL) begin
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debug_sig <= 7;
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address <= read_data[`hed_start:`hed_end];
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mem_func <= `GET_CONTENTS;
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mem_execute <= 1;
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state <= EXE_INIT_WRIT_TEL;
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end else begin
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error <= `ERROR_TEL_NOT_CELL;
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exec_func <= EXE_FUNC_ERROR;
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state <= EXE_ERROR_INIT;
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end
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end else begin
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mem_data <= read_data;
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mem_tag <= read_data[`tag_start:`tag_end]; // read first 4 bits and store into tag for easier access
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opcode <= read_data[`hed_start:`hed_end];
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b <= read_data[`tel_start:`tel_end];
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func_tag[1] <= execute_data[`tag_end];
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state <= EXE_INIT_DECODE;
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end
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end else begin
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mem_func <= 0;
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mem_execute <= 0;
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end
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end
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EXE_INIT_WRIT_TEL: begin
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if (mem_ready) begin
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debug_sig <= 22;
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write_addr_reg <= execute_address;
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mem_execute <= 1;
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write_data <= {execute_data[`tag_start:`tag_end],
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execute_data[`hed_start:`hed_end],
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18'b0,address};//data[`tel_start:`tel_end]};
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address <= execute_address;
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mem_func <= `SET_CONTENTS;
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mem_execute <= 1;
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state <= EXE_INIT_READ_TEL;
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end else begin
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mem_func <= 0;
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mem_execute <= 0;
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@ -295,7 +321,7 @@ module execute (
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state <= EXE_STACK_INIT;
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end else begin
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// Throw error invalid increment formulation
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error <= `ERROR_INVALID_B;
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error <= `ERROR_INVALID_B_CELL;
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exec_func <= EXE_FUNC_ERROR;
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state <= EXE_ERROR_INIT;
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end
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@ -310,7 +336,8 @@ module execute (
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state <= EXE_STACK_INIT;
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end else begin
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// Throw error invalid increment formulation
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error <= `ERROR_INVALID_B;
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debug_sig <= 16;
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error <= `ERROR_INVALID_B_INCR;
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exec_func <= EXE_FUNC_ERROR;
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state <= EXE_ERROR_INIT;
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end
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@ -384,7 +411,8 @@ module execute (
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EXE_SLOT_INIT: begin
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b <= (read_data[`tel_start:`tel_end]<<1) | 1;
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address <= execute_data[`hed_start:`hed_end]; // Read subject
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subject <= {execute_data[`hed_tag],execute_data[`hed_start:`hed_end]};
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subject <= execute_data[`hed_start:`hed_end];
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subject_tag <= execute_data[`hed_tag];
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mem_reg <= execute_data;
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state <= EXE_SLOT_PREP;
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mem_execute <= 1;
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@ -410,9 +438,9 @@ module execute (
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mem_execute <= 1;
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write_data <= {
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6'b000000,
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subject[`noun_width],
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subject_tag,
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1'b1,
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subject[`noun_width-1:0],
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subject,
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`NIL};
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//1'b0,
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//read_data[62:0]};
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@ -428,7 +456,8 @@ module execute (
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if (b[`noun_width-1] == 0) begin
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if(read_data[`hed_tag] == `CELL) begin
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address <= read_data[`hed_start:`hed_end];
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subject <= {read_data[`hed_tag],read_data[`hed_start:`hed_end]};
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subject <= read_data[`hed_start:`hed_end];
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subject_tag <= read_data[`hed_tag];
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mem_func <= `GET_CONTENTS;
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mem_execute <= 1;
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state <= EXE_SLOT_CHECK;
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@ -441,7 +470,7 @@ module execute (
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write_data <= {
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6'b000000,
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read_data[`hed_tag],
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1'b0,
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1'b1,
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read_data[`hed_start:`hed_end],
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`NIL};
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//28'h0000};
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@ -454,7 +483,8 @@ module execute (
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end else begin
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if(read_data[`tel_tag] == `CELL) begin
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address <= read_data[`tel_start:`tel_end];
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subject <= {read_data[`tel_tag],read_data[`tel_start:`tel_end]};
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subject <= read_data[`tel_start:`tel_end];
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subject_tag <= read_data[`tel_tag];
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mem_func <= `GET_CONTENTS;
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mem_execute <= 1;
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state <= EXE_SLOT_CHECK;
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@ -467,7 +497,7 @@ module execute (
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write_data <= {
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6'b000000,
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read_data[`tel_tag],
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1'b0,
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1'b1,
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read_data[`tel_start:`tel_end],
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`NIL};
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//28'h0000};
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@ -661,7 +691,8 @@ module execute (
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address <= func_addr;
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mem_func <= `SET_CONTENTS;
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mem_execute <= 1;
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write_data <= {8'b00000011,
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write_data <= {6'b000000,
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2'b11,
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27'h0, read_data[`hed_tag],
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`NIL};
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state <= EXE_CELL_WRITE_WAIT;
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@ -705,9 +736,13 @@ module execute (
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EXE_INCR_A: begin
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if (mem_ready) begin
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if (read_data[`hed_tag] == `CELL) begin
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error <= `ERROR_INVALID_B;
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exec_func <= EXE_FUNC_ERROR;
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state <= EXE_ERROR_INIT;
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debug_sig <= 12;
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stack_P <= trav_P;
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exec_func <= EXE_FUNC_STACK;
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state <= EXE_STACK_INIT;
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//error <= `ERROR_INVALID_B_INCR;
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//exec_func <= EXE_FUNC_ERROR;
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//state <= EXE_ERROR_INIT;
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end else begin
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address <= func_addr;
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write_addr_reg <= func_addr;
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@ -774,7 +809,7 @@ module execute (
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EXE_FUNC_STACK: begin
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case (state)
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EXE_STACK_INIT: begin
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EXE_STACK_INIT: begin // D0
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address <= stack_P;
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trav_P <= stack_P;
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mem_func <= `GET_CONTENTS;
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@ -782,8 +817,9 @@ module execute (
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state <= EXE_STACK_READ_WAIT;
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end
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EXE_STACK_READ_WAIT: begin
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EXE_STACK_READ_WAIT: begin // D1
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if (mem_ready) begin
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read_data_reg <= read_data;
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stack_a <= read_data[`hed_start:`hed_end];
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address <= read_data[`tel_start:`tel_end];
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stack_P_tel <= read_data[`tel_start:`tel_end];
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@ -799,22 +835,23 @@ module execute (
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end
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end
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EXE_STACK_READ_WAIT_2: begin
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EXE_STACK_READ_WAIT_2: begin //D2
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if (mem_ready) begin
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stack_b <= read_data[`tel_start:`tel_end];
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stack_mem_tag_2 <= read_data[`tag_start:`tag_end];
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stack_b <= read_data_reg[`tel_start:`tel_end];
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stack_mem_tag_2 <= read_data_reg[`tag_start:`tag_end];
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address <= stack_P;
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write_data <= {
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stack_mem_tag_1[7],
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3'b000,
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read_data[`tag_start-1],
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read_data_reg[`tag_start-1],
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stack_mem_tag_1[2],
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read_data[`tag_start-3],
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read_data_reg[`tag_start-3],
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stack_mem_tag_1[0],
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read_data[`hed_start:`hed_end],
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read_data_reg[`hed_start:`hed_end],
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trav_B
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}; //Set data to visited tel and b in tel while swaping opcode and a
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if(trav_B == `NIL) debug_sig <= 32;
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mem_func <= `SET_CONTENTS;
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mem_execute <= 1;
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state <= EXE_STACK_WRITE_WAIT;
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@ -824,7 +861,7 @@ module execute (
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end
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end
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EXE_STACK_WRITE_WAIT: begin
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EXE_STACK_WRITE_WAIT: begin //D3
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if (mem_ready) begin
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address <= stack_P_tel;
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write_data <= {
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@ -850,7 +887,7 @@ module execute (
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end
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end
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EXE_STACK_CHECK_NEXT: begin
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EXE_STACK_CHECK_NEXT: begin //D4
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if (mem_ready) begin
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address <= read_data[`tel_start:`tel_end];
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mem_func <= `GET_CONTENTS;
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@ -863,7 +900,7 @@ module execute (
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end
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end
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EXE_STACK_CHECK_WAIT: begin
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EXE_STACK_CHECK_WAIT: begin //D5
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if (mem_ready) begin
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if((read_data[`hed_start:`hed_end] < 0) || (read_data[`hed_start:`hed_end] > 11)) begin //If invalid opcode
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error <= `ERROR_INVALID_OPCODE;
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@ -873,10 +910,8 @@ module execute (
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exec_func <= EXE_FUNC_SLOT;
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state <= EXE_SLOT_INIT;
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a <= stack_a;
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func_tag[0] <= stack_mem_tag_1[1];
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b <= read_data[`tel_start:`tel_end];
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func_tag[1] <= read_data[`tag_end+1];
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func_addr <= stack_P_tel;
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trav_P <= stack_P_tel;
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@ -887,10 +922,8 @@ module execute (
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exec_func <= EXE_FUNC_CONSTANT;
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state <= EXE_CONSTANT_INIT;
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a <= stack_a;
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func_tag[0] <= stack_mem_tag_1[1];
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b <= read_data[`tel_start:`tel_end];
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func_tag[1] <= read_data[`tag_end+1];
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func_addr <= stack_P_tel;
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trav_P <= stack_P_tel;
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@ -898,6 +931,7 @@ module execute (
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func_return_exec_func <= EXE_FUNC_STACK;
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func_return_state <= EXE_STACK_POP;
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end else begin
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debug_sig<=33;
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stack_P <= stack_P_tel;
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state <= EXE_STACK_INIT;
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end
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@ -907,7 +941,7 @@ module execute (
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end
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end
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EXE_STACK_POP: begin
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EXE_STACK_POP: begin //D6
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if (mem_ready) begin
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trav_P <= trav_B;
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address <= trav_P;
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@ -920,10 +954,9 @@ module execute (
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end
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end
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EXE_STACK_POP_READ: begin
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EXE_STACK_POP_READ: begin //D7
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if (mem_ready) begin
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a <= read_data[`hed_start:`hed_end];
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func_tag[0] <= read_data[`tag_end];
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address <= trav_B;
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mem_func <= `GET_CONTENTS;
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@ -935,7 +968,7 @@ module execute (
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end
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end
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EXE_STACK_POP_WAIT: begin
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EXE_STACK_POP_WAIT: begin //D8
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if (mem_ready) begin
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opcode <= read_data[`hed_start:`hed_end];
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trav_B <= read_data[`tel_start:`tel_end];
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@ -996,7 +1029,7 @@ module execute (
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end
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end
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EXE_STACK_POP_ERR: begin
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EXE_STACK_POP_ERR: begin // D9
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if (mem_ready) begin
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$stop;
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end else begin
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@ -25,10 +25,11 @@
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// Error Definitions
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`define ERROR_TEL_NOT_CELL 8'h01
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`define ERROR_INVALID_OPCODE 8'h02
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`define ERROR_INVALID_B 8'h03
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`define ERROR_INVALID_SLOT 8'h04
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`define ERROR_INVALID_SLOT_HED 8'h05
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`define ERROR_INVALID_SLOT_TEL 8'h06
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`define ERROR_INVALID_B_CELL 8'h03
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`define ERROR_INVALID_B_INCR 8'h04
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`define ERROR_INVALID_SLOT 8'h05
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`define ERROR_INVALID_SLOT_HED 8'h06
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`define ERROR_INVALID_SLOT_TEL 8'h07
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`endif
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@ -51,7 +51,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
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output reg [`noun_tag_width - 1:0] noun_tag_gp;
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// [[50 51] [2 [0 3] [1 [4 0 1]]]]
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reg [0:0] debug_flag;
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// Traversal Registers needed
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reg [`noun_width - 1:0] trav_P;
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@ -88,6 +87,7 @@ module mem_traversal(power, clk, rst, start_addr, execute,
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SYS_EXECUTE_READ_TEL = 4'h2,
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SYS_EXECUTE_WAIT = 4'h3,
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SYS_EXECUTE_DECODE = 4'h4,
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SYS_EXECUTE_READ_ADDR = 4'h5,
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SYS_EXECUTE_ERROR = 4'hF;
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always@(posedge clk or negedge rst) begin
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@ -101,7 +101,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
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mem_execute <= 0;
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debug_sig <= 0;
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mux_controller <= 0;
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debug_flag <=0;
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end
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else if (execute) begin
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@ -127,10 +126,14 @@ module mem_traversal(power, clk, rst, start_addr, execute,
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state <= SYS_EXECUTE_READ_TEL;
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end
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else begin
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address <= mem_data[`tel_start:`tel_end];
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mem_func <= `GET_CONTENTS;
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mem_execute <= 1;
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execute_address <= mem_addr;
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execute_data <= mem_data;
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execute_tag <= mem_tag;
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mux_controller <= 1;
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debug_sig <= 3;
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state <= SYS_EXECUTE_WAIT;
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end
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end
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@ -138,9 +141,9 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
SYS_EXECUTE_READ_HED: begin
|
||||
if(mem_ready) begin
|
||||
if(read_data[`execute_bit]==1) begin
|
||||
debug_flag <=1;
|
||||
// If we need to execute the hed
|
||||
$stop;
|
||||
sys_func <= SYS_FUNC_TRAVERSE;
|
||||
state <= SYS_TRAVERSE_INIT;
|
||||
end
|
||||
else begin
|
||||
if (mem_data_gp[`tel_tag]==`CELL) begin
|
||||
@ -154,10 +157,14 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
else begin
|
||||
// if not executing hed and parent then pass data to
|
||||
// the execute block
|
||||
address <= mem_data_gp[`tel_start:`tel_end];
|
||||
mem_func <= `GET_CONTENTS;
|
||||
mem_execute <= 1;
|
||||
execute_address <= mem_addr;
|
||||
execute_data <= mem_data;
|
||||
execute_tag <= mem_tag;
|
||||
mux_controller <= 1;
|
||||
debug_sig <= 2;
|
||||
state <= SYS_EXECUTE_WAIT;
|
||||
end
|
||||
end
|
||||
@ -173,16 +180,26 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
if(mem_ready) begin
|
||||
if(read_data[`execute_bit]==1) begin
|
||||
// If we need to execute the tel
|
||||
$stop;
|
||||
sys_func <= SYS_FUNC_TRAVERSE;
|
||||
state <= SYS_TRAVERSE_INIT;
|
||||
end
|
||||
else begin
|
||||
// if not executing hed and parent then pass data to
|
||||
// the execute block
|
||||
debug_sig <= 1;
|
||||
if(trav_B != `NIL) mem_addr <= trav_B;
|
||||
execute_address <= mem_addr;
|
||||
execute_data <= mem_data;
|
||||
execute_tag <= mem_tag;
|
||||
execute_data <= {mem_tag,hed,tel};//read_data;
|
||||
execute_tag <= mem_tag;//read_data[`tag_start:`tag_end];
|
||||
//execute_data <= mem_data;
|
||||
//execute_tag <= mem_tag;
|
||||
mux_controller <= 1;
|
||||
state <= SYS_EXECUTE_WAIT;
|
||||
//address <= mem_addr;
|
||||
//mem_func <= `GET_CONTENTS;
|
||||
//mem_execute <= 1;
|
||||
|
||||
//state <= SYS_EXECUTE_READ_ADDR;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
@ -192,8 +209,24 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
|
||||
end
|
||||
|
||||
SYS_EXECUTE_READ_ADDR: begin
|
||||
if(mem_ready) begin
|
||||
debug_sig <= 6;
|
||||
if(trav_B != `NIL) mem_addr <= trav_B;
|
||||
execute_address <= mem_addr;
|
||||
execute_data <= {mem_tag,hed,tel};//read_data;
|
||||
execute_tag <= mem_tag;//read_data[`tag_start:`tag_end];
|
||||
mux_controller <= 1;
|
||||
state <= SYS_EXECUTE_WAIT;
|
||||
end else begin
|
||||
mem_func <= 0;
|
||||
mem_execute <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
SYS_EXECUTE_WAIT: begin
|
||||
if(execute_finished) begin
|
||||
debug_sig <= 0;
|
||||
sys_func = execute_return_sys_func;
|
||||
state = execute_return_state;
|
||||
mux_controller <= 0;
|
||||
@ -212,7 +245,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
SYS_FUNC_READ: begin
|
||||
case(state)
|
||||
SYS_READ_INIT: begin
|
||||
debug_flag <=0;
|
||||
if(mem_addr == 1023) begin // mem_addr is only max when you reach the end and use trav_b's inital value
|
||||
is_finished_reg <= 1;
|
||||
end
|
||||
@ -234,11 +266,17 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
|
||||
hed <= read_data[`hed_start:`hed_end];
|
||||
tel <= read_data[`tel_start:`tel_end];
|
||||
//if tel is nil do soemthing?
|
||||
// If cell is marked for execution
|
||||
if(read_data[`execute_bit] == 1) begin
|
||||
if (read_data[`tel_start:`tel_end] == `NIL) begin
|
||||
sys_func <= SYS_FUNC_TRAVERSE;
|
||||
state <= SYS_TRAVERSE_INIT;
|
||||
end else begin
|
||||
sys_func <= SYS_FUNC_EXECUTE;
|
||||
state <= SYS_EXECUTE_INIT;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
sys_func <= SYS_FUNC_TRAVERSE;
|
||||
state <= SYS_TRAVERSE_INIT;
|
||||
@ -258,7 +296,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
SYS_FUNC_WRITE: begin
|
||||
case(state)
|
||||
SYS_WRITE_INIT: begin
|
||||
debug_flag <=0;
|
||||
address <= mem_addr;
|
||||
write_data <= {mem_tag, hed, tel};
|
||||
mem_func <= `SET_CONTENTS;
|
||||
@ -285,7 +322,6 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
SYS_FUNC_TRAVERSE: begin
|
||||
case(state)
|
||||
SYS_TRAVERSE_INIT: begin
|
||||
debug_flag <=1;
|
||||
case(mem_tag[1:0])
|
||||
`CELL_CELL: begin
|
||||
if(mem_tag[3:2] == 2'b00) begin // if the hed cell hasn't been visited we push into it
|
||||
@ -323,8 +359,13 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
end
|
||||
else if(mem_tag[3:2] == 2'b11) begin // if both were visited
|
||||
// Set the command after write to pop
|
||||
if(mem_tag[7] == 1) begin // If we still need to execute
|
||||
write_return_sys_func <= SYS_FUNC_EXECUTE;
|
||||
write_return_state <= SYS_EXECUTE_INIT;
|
||||
end else begin
|
||||
write_return_sys_func <= SYS_FUNC_TRAVERSE;
|
||||
write_return_state <= SYS_TRAVERSE_POP;
|
||||
end
|
||||
|
||||
mem_tag[3:2] <= 2'b00;
|
||||
|
||||
@ -346,6 +387,7 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
`ATOM_CELL: begin
|
||||
if(mem_tag[2] == 1'b0) begin // if both were visited
|
||||
|
||||
debug_sig <= 1;
|
||||
|
||||
// Set the command after write to traverse the tel
|
||||
write_return_sys_func <= SYS_FUNC_TRAVERSE;
|
||||
@ -364,9 +406,17 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
state <= SYS_WRITE_INIT;
|
||||
end
|
||||
else begin
|
||||
debug_sig <= 2;
|
||||
// Set the command after write to pop
|
||||
if(mem_tag[7] == 1) begin // If we still need to execute
|
||||
write_return_sys_func <= SYS_FUNC_EXECUTE;
|
||||
write_return_state <= SYS_EXECUTE_INIT;
|
||||
end else begin
|
||||
write_return_sys_func <= SYS_FUNC_TRAVERSE;
|
||||
write_return_state <= SYS_TRAVERSE_POP;
|
||||
end
|
||||
//write_return_sys_func <= SYS_FUNC_TRAVERSE;
|
||||
//write_return_state <= SYS_TRAVERSE_POP;
|
||||
|
||||
mem_tag[3:2] <= 2'b00;
|
||||
|
||||
@ -400,8 +450,15 @@ module mem_traversal(power, clk, rst, start_addr, execute,
|
||||
end
|
||||
else begin
|
||||
// Set the command after write to pop
|
||||
if(mem_tag[7] == 1) begin // If we still need to execute
|
||||
write_return_sys_func <= SYS_FUNC_EXECUTE;
|
||||
write_return_state <= SYS_EXECUTE_INIT;
|
||||
end else begin
|
||||
write_return_sys_func <= SYS_FUNC_TRAVERSE;
|
||||
write_return_state <= SYS_TRAVERSE_POP;
|
||||
end
|
||||
//write_return_sys_func <= SYS_FUNC_TRAVERSE;
|
||||
//write_return_state <= SYS_TRAVERSE_POP;
|
||||
|
||||
mem_tag[3:2] <= 2'b00;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user