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Add dummy component to each plate case

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This works around a segfault in Pcbdraw which prevents renders in the
edge case where a PCB file has no module.
This commit is contained in:
Pierre Chevalier 2021-03-12 00:11:31 +00:00
parent d742fec71e
commit f509db5369
10 changed files with 217782 additions and 7 deletions
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217694
0.2/bling/#ferris_case-Edge_Cuts.dxf Normal file
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File diff suppressed because it is too large Load Diff

12
0.2/bling/cases/mid_profile/bottom_plate_with_puck.kicad_pcb
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@ -5,7 +5,7 @@
(drawings 40)
(tracks 0)
(zones 0)
(modules 0)
(modules 1)
(nets 1)
)
@ -109,6 +109,16 @@
(uvia_drill 0.1)
)
(module dummy:dummy (layer F.Cu) (tedit 604AAE8F) (tstamp 604AAECA)
(at 12 12)
(fp_text reference dummy (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)
(gr_circle (center 67.790402 38.02) (end 46.780402 37.89) (layer Edge.Cuts) (width 0.05) (tstamp 6049EA61))
(gr_arc (start 61.59 173.76) (end 105.638 99.588735) (angle -15.4) (layer Cmts.User) (width 0.05) (tstamp 6049EA60))
(gr_line (start 106.1 51.84) (end 106.1 19.059419) (layer Edge.Cuts) (width 0.05) (tstamp 6049EA5F))

12
0.2/bling/cases/mid_profile/bottom_plate_without_puck.kicad_pcb
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@ -5,7 +5,7 @@
(drawings 39)
(tracks 0)
(zones 0)
(modules 0)
(modules 1)
(nets 1)
)
@ -109,6 +109,16 @@
(uvia_drill 0.1)
)
(module dummy:dummy (layer F.Cu) (tedit 604AAE8F) (tstamp 604AAE84)
(at 12.1 12.3)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)
(gr_arc (start 61.59 173.76) (end 105.638 99.588735) (angle -15.4) (layer Cmts.User) (width 0.05) (tstamp 6049EA60))
(gr_line (start 106.1 51.84) (end 106.1 19.059419) (layer Edge.Cuts) (width 0.05) (tstamp 6049EA5F))
(gr_circle (center 87.049819 19.4) (end 88.149819 19.42) (layer Edge.Cuts) (width 0.05) (tstamp 6049EA5E))

3
0.2/bling/cases/mid_profile/fp-lib-table Normal file
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@ -0,0 +1,3 @@
(fp_lib_table
(lib (name dummy)(type KiCad)(uri ${KIPRJMOD}/../../../../fp/dummy.pretty)(options "")(descr ""))
)

12
0.2/bling/cases/mid_profile/mid_plate.kicad_pcb
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@ -5,7 +5,7 @@
(drawings 32)
(tracks 0)
(zones 0)
(modules 0)
(modules 1)
(nets 1)
)
@ -109,6 +109,16 @@
(uvia_drill 0.1)
)
(module dummy:dummy (layer F.Cu) (tedit 604AAE8F) (tstamp 604AB172)
(at 12 12)
(fp_text reference dummy (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)
(gr_arc (start 15.089318 406.95507) (end 82.995848 94.415389) (angle -12.12538542) (layer Edge.Cuts) (width 0.05) (tstamp 6049E573))
(gr_arc (start 106.708 97.938735) (end 105.638 99.588735) (angle -90.6) (layer Edge.Cuts) (width 0.05) (tstamp 6049E572))
(gr_arc (start 106.708 97.938735) (end 102.7 102.6) (angle -98.1305031) (layer Edge.Cuts) (width 0.05) (tstamp 6049E571))

12
0.2/bling/cases/mid_profile/top_left_plate_with_puck.kicad_pcb
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@ -5,7 +5,7 @@
(drawings 124)
(tracks 0)
(zones 0)
(modules 0)
(modules 1)
(nets 1)
)
@ -109,6 +109,16 @@
(uvia_drill 0.1)
)
(module dummy:dummy (layer F.Cu) (tedit 604AAE8F) (tstamp 604AAF5A)
(at 12 12)
(fp_text reference dummy (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)
(gr_line (start 107.092178 98.972178) (end 94.967822 91.972178) (layer Edge.Cuts) (width 0.05) (tstamp 6049E028))
(gr_line (start 114.092178 86.847822) (end 107.092178 98.972178) (layer Edge.Cuts) (width 0.05))
(gr_line (start 101.967822 79.847822) (end 114.092178 86.847822) (layer Edge.Cuts) (width 0.05))

12
0.2/bling/cases/mid_profile/top_left_plate_without_puck.kicad_pcb
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@ -5,7 +5,7 @@
(drawings 118)
(tracks 0)
(zones 0)
(modules 0)
(modules 1)
(nets 1)
)
@ -109,6 +109,16 @@
(uvia_drill 0.1)
)
(module dummy:dummy (layer F.Cu) (tedit 604AAE8F) (tstamp 604AAF6D)
(at 12 12)
(fp_text reference dummy (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)
(gr_line (start 69 68.5) (end 69 54.5) (layer Edge.Cuts) (width 0.05) (tstamp 6049EB3F))
(gr_line (start 107.092178 98.972178) (end 94.967822 91.972178) (layer Edge.Cuts) (width 0.05) (tstamp 6049E028))
(gr_line (start 114.092178 86.847822) (end 107.092178 98.972178) (layer Edge.Cuts) (width 0.05))

12
0.2/bling/cases/mid_profile/top_right_plate_with_puck.kicad_pcb
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@ -5,7 +5,7 @@
(drawings 117)
(tracks 0)
(zones 0)
(modules 0)
(modules 1)
(nets 1)
)
@ -109,6 +109,16 @@
(uvia_drill 0.1)
)
(module dummy:dummy (layer F.Cu) (tedit 604AAE8F) (tstamp 604AAF83)
(at 12 12)
(fp_text reference dummy (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)
(gr_line (start 107.092178 98.972178) (end 94.967822 91.972178) (layer Edge.Cuts) (width 0.05) (tstamp 6049E028))
(gr_line (start 114.092178 86.847822) (end 107.092178 98.972178) (layer Edge.Cuts) (width 0.05))
(gr_line (start 101.967822 79.847822) (end 114.092178 86.847822) (layer Edge.Cuts) (width 0.05))

12
0.2/bling/cases/mid_profile/top_right_plate_without_puck.kicad_pcb
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@ -5,7 +5,7 @@
(drawings 111)
(tracks 0)
(zones 0)
(modules 0)
(modules 1)
(nets 1)
)
@ -109,6 +109,16 @@
(uvia_drill 0.1)
)
(module dummy:dummy (layer F.Cu) (tedit 604AAE8F) (tstamp 604AAF97)
(at 12 12)
(fp_text reference dummy (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)
(gr_line (start 69 68.5) (end 69 54.5) (layer Edge.Cuts) (width 0.05) (tstamp 6049EB3F))
(gr_line (start 107.092178 98.972178) (end 94.967822 91.972178) (layer Edge.Cuts) (width 0.05) (tstamp 6049E028))
(gr_line (start 114.092178 86.847822) (end 107.092178 98.972178) (layer Edge.Cuts) (width 0.05))

8
fp/dummy.pretty/dummy.kicad_mod Normal file
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@ -0,0 +1,8 @@
(module dummy (layer F.Cu) (tedit 604AAE8F)
(fp_text reference dummy (at 0 0.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value dummy (at 0 -0.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
)